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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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UVMC 2.3.0 Library
UVMC Mar 15, 2015 html
Does Design Size Influence First Silicon Success?
Planning, Measurement and Analysis Mar 11, 2015 Harry Foster Article
Small, Maintainable Tests
UVM - Universal Verification Methodology Mar 11, 2015 Ashley Winn - Sondrel Ic Design Services Article
Coverage Data Exchange is No Robbery…Or is It?
Coverage Mar 03, 2015 Darron May pdf
Coverage Data Exchange is No Robbery…Or is It?
Coverage Mar 03, 2015 Darron May pdf
Coverage Data Exchange is No Robbery…Or is It?
Coverage Mar 03, 2015 Darron May Paper
Boosting Regression Throughput by Reusing Setup Phase Simulation
Simulation Mar 03, 2015 Rohit Jain pdf
Boosting Regression Throughput by Reusing Setup Phase Simulation
Simulation Mar 03, 2015 Rohit Jain Paper
Are You Smarter Than Your Testbench? With a Little Work You Can Be
UVM - Universal Verification Methodology Mar 03, 2015 Rich Edelman Paper
Are You Smarter Than Your Testbench? With a Little Work You Can Be
UVM - Universal Verification Methodology Mar 03, 2015 Rich Edelman pdf
UVM Sans UVM: An Approach to Automating UVM Testbench Writing
UVM - Universal Verification Methodology Mar 02, 2015 Rich Edelman pdf
UVM Sans UVM: An Approach to Automating UVM Testbench Writing
UVM - Universal Verification Methodology Mar 02, 2015 Rich Edelman Paper

January 2015

Coverage Cookbook - Japanese Release
Coverage Jan 14, 2015 pdf

December 2014

Introduction to Questa X-Check
Formal Verification Dec 20, 2014 Doug Smith Webinar

November 2014

Introduction to Questa CDC
Clock-Domain Crossing Nov 12, 2014 Doug Smith Webinar
Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide
Verification IP Nov 01, 2014 Prashant Dixit - Siemens Eda Article
Fast Track to Productivity Using Questa Verification IP
Verification IP Nov 01, 2014 Dave Aerne Article
Cache Coherent Interface Verification IP
Verification IP Nov 01, 2014 Amit Kumar Jain - Siemens Eda Article
Hey You, Design Engineer!
SystemVerilog Nov 01, 2014 Josh Rensch - Siemens Eda Article
Please! Can Someone Make UVM Easier to Use?
UVM - Universal Verification Methodology Nov 01, 2014 Rich Edelman Article
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench
UVM - Universal Verification Methodology Nov 01, 2014 Sundar Raman Arunachalam - Verikwest Systems Article
Increase Verification Productivity with Questa UVM Debug
Debug Nov 01, 2014 Dr. Mike Bartley Article

October 2014

Questa Coverage Closure
Coverage Oct 22, 2014 Thomas Ellis Demo
Introduction to Questa CoverCheck
Formal Verification Oct 16, 2014 Doug Smith Webinar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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