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September 2021 - Volume 17 Issue 2 (7)

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Show Less

January 2019

ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

December 2018

Slaying the UVM Reuse Dragon
Standards Dec 12, 2018 Bob Oden Article
Full-Featured SOC Debug Cross-Triggering
Simulation Dec 10, 2018 Verification Methodology Team Article

November 2018

FPGA Verification Challenges and Opportunities
FPGA Verification Nov 28, 2018 Harry Foster Article
Building a Better Virtual Sequence with Portable Stimulus
Standards Nov 28, 2018 Matthew Ballance Article
Simplifying Mixed-Signal Verification
Analog Mixed-Signal Nov 28, 2018 Article

October 2018

Functional Verification Study - 2018
Planning, Measurement and Analysis Oct 15, 2018 Harry Foster Session
How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
Functional Safety Oct 04, 2018 Verification Horizons Article
A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
Functional Safety Oct 04, 2018 Verification Horizons Article
Emulation Based Approach to ISO 26262 Compliant Processors Design
Standards Oct 04, 2018 Verification Horizons Article
AMS Verification for High Reliability and Safety Critical Applications
Simulation Oct 04, 2018 Verification Horizons Article

September 2018

UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick pdf
UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick Webinar

July 2018

Building An Integrated Verification Flow
Planning, Measurement and Analysis Jul 26, 2018 Neil Johnson pdf
AMS Verification Methodology for GPUs in AI and Deep Learning Applications
Analog Mixed-Signal Jul 26, 2018 pdf

June 2018

Comprehensive CDC Verification with Advanced Hierarchical Data Models
Clock-Domain Crossing Jun 29, 2018 Ping Yeung Article
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Standards Jun 29, 2018 Matthew Ballance Article
Coverage Driven Verification of NVMe Using Questa VIP (QVIP)
Verification IP Jun 29, 2018 Anurag Singh - Siemens Eda Article
Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
Low Power Jun 29, 2018 Progyna Khondkar Article
Complex Addressable Registers in Mission Critical Applications
Simulation Jun 29, 2018 Ishanee Bajpai - Agnisys Article
RTL Glitch Verification
Questa Design Solutions Jun 29, 2018 Ajay Daga - Fishtail Design Automation Article

May 2018

What is Formal, Anyway
Formal Verification May 14, 2018 pdf

April 2018

Running Simulations
UVM Framework Apr 16, 2018 Jonathan Craft pdf
Running Simulations
UVM Framework Apr 16, 2018 Jonathan Craft Session
Basic Abstraction Techniques
Formal Verification Apr 14, 2018 pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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