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March 2016 - Volume 12 Issue 1 (9)

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June 2013 - Volume 9 Issue 2 (8)

June 2017 - Volume 13 Issue 2 (8)

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June 2012 - Volume 8 Issue 2 (7)

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November 2014 - Volume 10 Issue 3 (7)

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September 2021 - Volume 17 Issue 2 (7)

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June 2018 - Volume 14 Issue 2 (6)

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March 2023 - Volume 19 Issue 1 (6)

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February 2013 - Volume 9 Issue 1 (5)

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November 2020 - Volume 16 Issue 3 (5)

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December 2022 - Volume 18 Issue 3 (4)

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June 2019 - Volume 15 Issue 2 (4)

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March 2014 - Volume 10 Issue 1 (4)

March 2018 - Volume 14 Issue 1 (4)

March 2021 - Volume 17 Issue 1 (4)

March 2022 - Volume 18 Issue 1 (4)

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November 2015 - Volume 11 Issue 3 (4)

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October 2013 - Volume 9 Issue 3 (4)

Parallel Simulation (4)

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1.2 (3)

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February 2019 - Volume 15 Issue 1 (3)

Formal Verification Apps (3)

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March 2017 - Volume 13 Issue 1 (3)

March 2020 - Volume 16 Issue 1 (3)

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November 2018 - Volume 14 Issue 3 (3)

October 2012 - Volume 8 Issue 3 (3)

Parallel Compile (3)

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December 2019 - Volume 15 Issue 3 (2)

Design Constraints (2)

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IEEE (2)

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July 2023 - Volume 19 Issue 2 (2)

Latch-Based Designs (2)

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LockGrab (2)

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MARLUG 2023 (2)

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Makefile (2)

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March 2015 - Volume 11 Issue 1 (2)

Memory Debug (2)

Metric Analyzers (2)

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Namespaces (2)

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Observer (2)

PHY (2)

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VA Live 2019 - Westford (2)

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December 2017 - Volume 13 Issue 3 (1)

Declarative Environment (1)

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IEEE 1149.1-2013 (1)

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October 2022

Part 1: The Global FPGA Semiconductor Market
Planning, Measurement and Analysis Oct 16, 2022 Harry Foster link

September 2022

SystemVerilog: Implicit handles
SystemVerilog Sep 06, 2022 Chris Spear link

August 2022

SystemVerilog: Class Member Visibility
SystemVerilog Aug 29, 2022 Chris Spear link

July 2022

The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Sumit Vishwakarma Article
Getting to Know Visualizer - Part II
Debug Jul 05, 2022 Rich Edelman Article
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article
Reflections on Users’ Experiences with SVA - Part II
SystemVerilog Jul 05, 2022 Ben Cohen Article
Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

June 2022

Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman Paper
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf
The Three Pillars of Intent-Focused Insight
Planning, Measurement and Analysis Jun 08, 2022 Harry Foster Webinar

May 2022

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar
Securing the Electronics Development Chain with IC Integrity Solutions
Formal Verification May 10, 2022 John Hallman Webinar

March 2022

The Best Verification Strategy You’ve Never Heard Of
Planning, Measurement and Analysis Mar 28, 2022 mp4
What Does the Sequence Say? Powering Productivity with Polymorphism
UVM - Universal Verification Methodology Mar 23, 2022 pdf
Confidently Sign-off any Low-Power Designs without Consequences
Low Power Mar 23, 2022 pdf
Path-based UPF Strategies Optimally Manage Power on your Designs
Low Power Mar 23, 2022 pdf
Formal 101: Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 Joe Hupcey Webinar
Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 pdf
Getting to Know Visualizer - Part I
Debug Mar 02, 2022 Rich Edelman Article
Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article
UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Espen Tallaksen - Emlogic Article

February 2022

Equivalence Checking for FPGA
Formal Verification Feb 25, 2022 Martin Rowe Webinar

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

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