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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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Verification IQ Nov 06, 2024 Ahmed Elkady - Siemens Eda pdf

October 2024

Celebrating the Approval of Portable Test and Stimulus Standard (PSS) 3.0
Portable Stimulus Oct 09, 2024 Dennis Brophy link
Increasing Fault Coverage with Siemens Functional Fault Grading Solutions
Functional Safety Oct 08, 2024 Ann Keffer pdf

September 2024

MARLUG - 2024
FPGA Verification Sep 18, 2024 Austin Mam Seminar
Jump-Start Your UVM Journey with UVM Framework (UVMF)
UVM Framework Sep 04, 2024 Dennis Brophy link

August 2024

Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman Paper
Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman pdf
Having Your Cake and Eating It Too: Programming UVM Sequences with DPI-C
UVM - Universal Verification Methodology Aug 29, 2024 Rich Edelman pdf
Advanced Analytics for Accelerating RDC Verification Closure
Reset-Domain Crossing Aug 13, 2024 Reetika - Siemens Eda link
Portable Stimulus and VIP: Like a Hand in a Glove
Portable Stimulus Aug 08, 2024 Tom Fitzpatrick link
Announcing Avery UCIe 2.0 Verification IP from Siemens EDA
Verification IP Aug 06, 2024 Gordon Allan link
UVM Framework Release 2023.4_2
UVM Framework Aug 05, 2024 Bob Oden tar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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