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INTRODUCTION
The Unified Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minimum gate-to-source voltage differential that is needed in CMOS devices to create a conducting path between the source and the drain terminals (known as threshold voltage) has been pushed to its limit. Leakage power is a function of the threshold voltage, and at smaller device geometries, its contribution to total energy dissipation becomes
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