Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices.
Given the major adoption of UVM across the globe and across the industry, advanced users are looking for tips and tricks to improve their productivity. UVM does define a structured framework for building complex testbenches. It is built on strong OOP principles and design patterns using underlying SystemVerilog language features. This strong OOP nature presents certain challenges to the end users. Recall that many Design-Verification (DV) engineers