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Welcome to our special DAC 2016 Edition of Verification Horizons.

As I’ve said many times, DAC is undoubtedly my favorite work-related week of the year. In giving us all the opportunity to see the amazing technology that Siemens EDA, our partners and even our competitors introduce and the chance to catch up with old friends and colleagues, it serves as an annual milestone by which we measure both the progress of our industry and the passing of time.

This year, DAC happens to follow closely on the heels of a personal milestone as well. By the time you read this, my son, David, will have graduated from high school. I hope you’ll forgive a little paternal pride and allow me to tell you that he completed high school as the valedictorian of his class and will be attending Georgetown University in the fall. His mother, sister and I are, as you can imagine, extremely proud of him. I feel in some ways like we’ve reached “tape out” with this amazing young man as he goes out into the world, but of course our job is nowhere near complete. And, fortunately, we still have the summer with him.

One challenge David will have that most of us probably didn’t even consider when we graduated high school is a world with actual self-driving cars. As with anything, this exciting new technology comes with its own set of pitfalls, many of which we may not even be aware of yet. Our first article, “How Formal Techniques Can Keep Hackers from Driving You into a Ditch,” by my colleague Joe Hupcey, our Questa Formal Product Manager, certainly lives up to its title. By walking you through a case study, Joe will first scare you and then reassure you that the proper use of formal technology can indeed protect your car, whether self-driving or automation-assisted, from being hacked, with potentially life-saving implications.

In “Simplifying HDCP Verification Using Questa VIP (QVIP),” my colleagues from the VIP team begin with an explanation of the High-Bandwidth Digital Content Protection (HDCP) protocol, which can be used to protect critical audio and video data from third parties. Next, they lay out some of the verification challenges inherent in such a multi-step protocol and then show how the Display QVIP components are ideally suited for verifying this important functionality. It also serves to show some of the usability improvements we’ve made to our QVIP library.

We round out our contributed articles in this issue with "No RTL Yet? No Problem: UVM Testing a SystemVerilog Fabric Model" by my long-time colleague Rich Edelman. This article was originally presented as a paper at DVCon-US in March, but it's so good we wanted to share it with you. Rather than your verification team needing to wait for an RTL model of the DUT, Rich shows how some of the more abstract SystemVerilog language constructs can be used to create a functional model against which you can begin building your UVM testbench and developing sequences that can be reused with the ultimate RTL model at both the block and system level.

We begin our Partners' Corner section with "Accelerating Networking Products to Market" by noted emulation expert Lauro Rizatti, a frequent contributor. In the article, Lauro walks us through the evolution of emulation for verifying a complex network SoC, such as an Ethernet switch, from in-circuit emulation (ICE), with its limited usability and complex cabling, to today's enterprise-wide reconfigurable emulation resource center using VirtuaLAB software.

Next, our friends at Barco-Silex enlighten us about “Physical Verification of FPGAs in Accordance with an Aerospace DO 254 Methodology Flow.” The article highlights the flexibility of their AVP254 modular test platform that allows tests to be developed with the RTL model and then reused as-is with the actual FPGA once it’s available.

In “Extending UVM Verification Models for the Analysis of Fault Injection Simulations,” our friends at IROC Technologies show how UVM can be used in an ISO 26262-compliant verification effort. With some clever use of UVM phases and the uvm_report_catcher, they incorporate their Fault Injection Database, which allows control and coverage of faults to be recorded, in accordance with ISO 26262.

Our last Partners’ Corner contribution, “Saving Time and Improving Quality with a Specification to Realization Flow” comes from our friends at Agnisys. Their ISequenceSpec™ (ISS) tool lets you specify a set of sequences to exercise your design and then transform these sequences into UVM sequences or other implementations. These UVM sequences are then imported into the Questa inFact Intelligent Testbench Automation solution as actions that become nodes in a graph-based representation of abstract stimulus for the DUT.

In our Consultants’ Corner, we have VerifWorks introducing a set of best practices in UVM to help you “Solve UVM Debug Problems with the UVM Vault.” The article shows how to take advantage of some built-in UVM features with which you may be unfamiliar to help you debug a variety of problems commonly encountered when using the UVM Factory. These techniques were featured in the UVM “Tips and Tricks” tutorial at DVCon-US back in March.

I’ve had the great fortune, as Editor, to share with you numerous stories about my family over the years, and it’s been fun to relate these anecdotes to various aspects of Functional Verification, however contrived those analogies may be. But now I think about my son, about whom I’ve shared stories of when I coached him in baseball, hiked with him in the Boy Scouts and shared the many ups and downs of our beloved Boston Red Sox and New England Patriots, and I am amazed at how much we have both changed over the past 10+ years that Verification Horizons has been published. He is about to embark toward horizons of his own, and I’m excited to see how things turn out for him.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons