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by Amit Tanwar and Manoj Manu, Questa VIP Engineering, Mentor Graphics
Because of the complexities involved in the entire design verification flow, a traditional Verification IP (VIP) tends to overlook the subtle aspects of the physical layer (PHY) verification, often leading to costly debug phases later in the verification cycle.
In addition, because of the several possible topologies in a PHY implementation, completely exercising the role and related functionality of a PHY becomes challenging for a traditional VIP.
Furthermore, the analog signaling and the homologous functionality of the physical layer in serial protocols, led the industry to define a common PHY that multiple protocols could use and that segregates the PHY logic from
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