by Mahak Singh, Design Engineer, Siddhartha Mukherjee, Sr. Design Engineer, Truechip
Conferences, discussions, or evaluations, engineers everywhere are asking the same questions:
How to achieve the maximum coverage with randomization? What level of cross coverage to be checked for?
Achieving maximum randomization and coverage, how much of verification cycle time hit will it cost? Can I control it?
Today, each verification component is loaded with modes and features. How can we use these modes or features to create the maximum possible scenarios, and still be able to control the potential run time.
With a variety of modes and options in your verification component you need a way to fire them randomly to stress test the DUT. Here comes the