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by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions
Abstract
The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects to demand more from the main interconnect or network-on-chip (NoC), which is thus becoming a key component of the system. Power management, multiple clocks, protocol conversions, security management, virtual address space, cache coherency are among the features that must be managed by main interconnect and that demand proper verification. In addition, IP reuse and NoC generation solutions have enabled the conception of new SoC architectures within months or even weeks.
Simple point-to-point scoreboard methodology is taught in most good verification methodology
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