Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications
In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
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Session Registration
Session Registration
Date and Time
- Wednesday, October 30th
- 9:00 AM US/Pacific
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Session Overview
High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
What You Will Learn
- What's new in HBM4
- Challenges involved in verifying advanced HBM generations
- Unique features in Siemens's HBM4 memory models
- Rambus's newly-announced HBM4 memory controller IP
Who Should Attend
- Design & Verification Engineers, Architects
- Managers and Directors for memory controllers
What/Which Products are Covered
- Siemens Avery HBM4 Verification IP
- Rambus HBM4 Memory Controller