Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP
In this webinar we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.
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Session Registration
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Session Overview
Design and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation, they need protocol accuracy from day one, and they need a predictable path to signoff while integration risks rise every quarter. This struggle has become a shared industry reality.
In this webinar we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs, with a shift-left in simulation and signoff using Avery Protocol VIP, CSS VIP, Software Aware VIP, Arm Fast Models and QEMU models.
This methodology helps teams reduce integration risks, shorten turnaround time, and gain system level confidence long before moving to emulation or prototypes. If you are a design or verification engineer, a firmware engineer or if you manage a team building next generation compute platforms, this is an event that will strengthen your technical path forward.
What You Will Learn
- Software Aware Verification IP and applications
- Block level / Subsystem Compliance Testing with Software Aware VIP
- Full CSS HW/FW/SW bring up and UEFI Bootup
- Advanced debug of Hardware/Firmware/Software
Who Should Attend
- Verification Managers and Directors
- Design and Verification Engineers
- Firmware/Software Engineers
Products Covered
- Avery Verification IP
- Software Aware VIP
- System VIP (CSS)
