Boosting Simulation Performance of UVM Registers in High Performance Systems

Registers and memory blocks are key parts of any design; a typical design could hold hundreds of them. Verifying the behavior of registers and memory blocks is an essential part in the verification process. There are many techniques for modeling and verifying hardware registers and memory blocks. In this paper, we focus on verifying hardware registers using register packages.

Verification and modeling of hardware registers and memory blocks via register packages is not a new trend. Many register packages from various vendors, written in different languages, currently exist and used in the industry. The Accellera VIP-TSC committee has made a significant progress in releasing the Universal Verification Methodology¹ defining standards for creation, integration, and extension of verification environments.

The UVM register library is an open-source library, being part of the UVM library, which allows modeling and verification of hardware registers and memory blocks. Yet, the way the UVM register library is currently designed to layer registers and memories transactions on top of bus transactions, well suits low speed buses. On the other hand, it may not be efficient for high performance buses introducing undesired simulation performance degradation.

Naming some of the UVM register library features:

• Address management.
• Modeling registers and memory blocks.
• Front door and back-door access to Device under Verification (DUV).
• Implicit and explicit prediction of registers and memory blocks values.
• Coverage model API.

Usually, the integration of a register library in a testbench environment requires four abstract steps:

1. building the register database
2. writing registers and memory blocks test sequences
3. configuring registers coverage as needed
4. integrating registers models and test sequences to the testbench verification components.

Building the Register Database

Although register models could be built-up manually, typically register models are automatically generated using register model generators, which prevent manual coding errors. There are a number of commercial UVM register generator tools that can capture register specification from spreadsheet, IP-XACT, and XML inputs. Below we provide a quick overview of the different UVM classes used to build your register database.