Efficient Modeling Styles and Methodology for Gate-Level Design Verification

The exploding complexity of IC systems have contributed to the increase in challenges to verifying these designs. It is not uncommon to find designs that contain anywhere from a few million gates to hundreds of millions of gates, straining the limits of functional verification based on traditional simulation technologies. In response, verification processes are evolving with the wide adoption of sophisticated techniques, such as formal verification, that reduce the amount of work required to achieve verification goals.

However, despite being one of the oldest verifications flows, gate-level simulations (also known as, GLS) remain an integral part of product design sign-off. Since gate-level verification depends so heavily on simulation, any improvements to simulation methodology and technology can go a long way toward improving the overall verification efficiency.

In this paper, we will discuss the various methodologies and flows available for gate-level timing simulations and the scenarios that each flow is suitable for. This will help designer/validation engineers understand what these flows mean and make informed decisions when setting up a gate-level validation process; such as, what different timing modes (zero delay, unit delay, negative delay, etc.) should be used under what circumstances.

This paper will also address the major pain points for gate-level validation engineers. These include efficiently improving debug of zero delay loops, X- tracing, and preventing zero-delay race conditions and feedback loops.

We will also touch upon methods to improve the validation of ATPG patterns and BIST tests. These tests often have a test set up phase, followed by multiple pattern test phases. We will discuss these different phases and how to best use them to create a methodology to improve the throughput of the serial and parallel ATPG pattern simulations.

Throughput gains achieved in the multi-day pattern simulations can not only provide a significant boost to verification productivity, but also help realize faster turn-around times during debug cycles.

Gate-Level Simulation Flow

We will start by describing some guidelines and recommendations to improve the overall throughput of gate-level simulations.

Netlist Compilations into Multiple Libraries

Often netlist compilation time is a significant bottleneck that affects turn-around times to validate any changes. Splitting the DUT and testbench compilation can be useful, especially if the intention is to run the DUT in an emulator. However, the DUT compile itself can slow down the turn-around time in simulation. A very efficient compilation flow for gate-level tests includes compiling each IP/block to its own work library.

This can be achieved quite easily by scripting individual compilation commands and executing them in parallel, say on several grid machines. It is imperative to ensure the compilations do not depend on each other for maximum gains. Implementation of such a parallel compilation flow at Customer A helped reduce the DUT compilation time from 3.5 hours down to 45 minutes for a 4.6X improvement in gate-level simulation compile times.

The design that was targeted for initial deployment of this flow was a full-chip multi-media SoC with ~50 million gates. The flow was easily ported for all future projects with a larger number of blocks/sub-systems and a larger number of gates. With Questa®, you can use the –work option to specify different work libraries at vlog/vcom compile time, and then use –L option to include these libraries during vopt time.