Portable Stimulus
The Portable Stimulus Standard (PSS) represents a transformative advancement in verification methodologies. At its essence, it is a standard that allows for the specification of verification intent a single time followed by its reapplication across various platforms, tools, and verification stages. Developed by the Accellera Systems Initiative, Portable Stimulus offers a unified framework for creating verification tests that can be effectively utilized across multiple verification environments and abstraction levels.
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Portable Stimulus White Paper
Better Stimulus Generation Through AI
This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Portable Stimulus Resources
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Better Stimulus Generation Through AI
As semiconductor designs grow increasingly complex, verification teams face mounting pressure to ensure design correctness while meeting aggressive time-to-market demands. While PSS offers powerful capabilities for creating reusable verification assets, there are perceived adoption limitations. This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Portable Stimulus Forum Discussion
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Introduction
The Portable Stimulus Standard (PSS) represents a transformative advancement in verification methodologies. At its essence, it is a standard that allows for the specification of verification intent a single time followed by its reapplication across various platforms, tools, and verification stages. Developed by the Accellera Systems Initiative, Portable Stimulus offers a unified framework for creating verification tests that can be effectively utilized across multiple verification environments and abstraction levels.
Rather than being restrained by the conventional approach of developing unique tests for simulation, emulation, or hardware validation, Portable Stimulus empowers verification engineers to describe their verification intentions in an abstract and declarative format. This abstract description is then seamlessly translated into precise correct-by-construction tests tailored for different verification platforms and environments, enabling true verification reuse.
By allowing verification engineers to write once and run anywhere, it offers seamless translation across diverse verification platforms, thereby reducing redundancy in test creation and ensuring a consistent verification approach across different project phases. This approach enhances coverage and quality, systematically exploring intricate scenarios and automatically generating comprehensive test cases to ensure better coverage of corner cases and verification completeness.
By automating the test generation process, PSS reduces manual coding efforts, accellerates test development and improves resource utilization efficiency. Moreover, its scalability adeptly manages the testing of complex modern SoC designs, supporting multi-threaded scenarios and handling sophisticated dependencies, making it adaptable across projects of varying sizes.
PSS models support creating multiple implementations of the generated scenarios, including Universal Verification Methodology (UVM) testbench environments, emulation platforms, FPGA prototypes, and post-silicon validation processes.