Is there an article which talks about c-uvm synchronization (without DPI) in an SoC testbench where CPU is involved.
I haven’t come across an article discussing C-UVM synchronization without mentioning the DPI, likely because the DPI is significantly more efficient compared to any other synchronization mechanism.
thank you
@dave_59
Could you please elaborate on other C/System-Verilog synchronization mechanisms?
Maybe what @abhi98911 meant somehow to a way of communication between the SV code and the C code running on the CPUs present in the SoC?
e.g. handling interrupt, running service routines.
yes. thats what i meant. I have edited my original statement to be more clear