Securing your FPGA Design from RTL through to the Bitstream

https://event.on24.com/wcc/r/4903067/6972EA1651CC867EA9FDEBE8B8C8588C

Date & Time

• Wednesday, April 23rd
• 08:00 AM | US/Pacific

This webinar will delve into the critical role of hardware security verification, outlining why it is essential for protecting modern FPGA designs from RTL through to the FPGA bitstream. It will stress the use of formal-based methods and FPGA bitstream security analysis as a rigorous approach to ensure the integrity and resilience of FPGA-based hardware designs. In addition, the presentation will provide an overview of a recommended hardware security flow, detailing the key stages and best practices in the process.

This webinar will briefly introduce practical tools such as the Siemens Analyze Architecture and VerifySecure technologies, highlighting how they support the overall security strategy.

In addition, we will introduce Bitwise (powered by Red Balloon Security) as a point-and-click assurance tool that delivers rapid security analysis and hardening of FPGA bitstreams. Bitwise validates whether security settings in a generated bitstream are correctly implemented in a FPGA design and provides a security score, without access to project design files or vendor source code.

These technologies operate synergistically and integrate with our previous security and assurance focused webinar - Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream.

What You Will Learn

• Security flow recommendations for FPGA designs
• Capabilities for RTL level security analysis
• Evaluate the security posture of the Bitstream.
• Add Hardening techniques to the Bitstream’s configuration engine
• Encrypt/Re-encrypt Bitstreams

Who Should Attend

• FPGA Design Engineers
• FPGA Verification Engineers
• Trust/Assurance Engineers
• Safety Engineers
• Security Engineers

Products Covered

• Siemens Analyze Architecture
• Siemens VerifySecure
• Red Balloon Security Bitwise