The “Formal 101” Series: Learn Formal the Easy Way
Everyone wants exhaustive verification, and thus people want to learn more about formal property checking flows and tools. But they either don’t where to start, or they are afraid that the learning curve will be protracted and confusing.
In this track, the sessions are designed to help anyone who is familiar with VHDL, Verilog, SystemC, or C++ quickly learn the basics of formal.
If you want get comfortable with the technological underpinnings of formal before diving in, start with this:
Forum Discussion - Formal