CDC Verification

For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SOC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis. For example, let’s consider two IP blocks that individually pass their static timing analysis. There are still potential design errors due to the asynchronous interaction of these two blocks. If data is asynchronously transferred between the two IP blocks, and the data changes values during the receiving flip-flop’s setup or hold-timing constraint, then the receiving flip-flop may enter into a metastable state. Hence, ensuring that the two asynchronous domains are properly designed with an appropriate synchronization scheme is critical to preventing the propagation of illegal metastable states through the design.

Furthermore, even with properly synchronized paths, it becomes necessary to verify that the non-deterministic latency introduced between multiple synchronizers does not reconverge in such a way as to create a design error. In the process of helping project teams deploy clock-domain crossing verification, we have observed a number of myths, misunderstandings, and costly mistakes. This Verification Academy track directly addresses these issues by introducing a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics for measuring success while identifying process areas requiring improvement.

This Verification Academy track is intended to be highly interactive-allowing the attendee to ask detailed questions concerning developing a successful clock-domain crossing (CDC) methodology.