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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home /
  • Walk

Walk

Walk

The Verification Academy has adopted 3 target audience classifications; Crawl, Walk and Run based upon the Evolving Capabilities Model introduced in the Evolving Verification Capabilities Course by Harry Foster.

The sessions listed below are targeted to the Walk audience and is considered: content is of general interest, particularly to managers, but also engineers.

Walk: Content is of general interest, particularly to managers, but also engineers.

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AMS Verification Methodology for GPUs in AI and Deep Learning Applications

DAC 2018 | AMS Verification Methodology for GPUs in AI and Deep Learning Applications

This session will provide an overview of the AI and deep learning applications using GPUs, the added complexities on AMS verification and the methodology used to address these verification challenges in efficient and predictable ways.

Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC Level

DAC 2018 | Clock-Domain Crossing with HDM - Enhanced Accuracy and Seamless Visibility at SOC level

CDC Analysis at SOC level involves huge challenges in terms of capacity, quality of results, and ease of debug, dependencies and ownership of IPs. The flagship SOC designs are typically the biggest and the most complex.

Data Mining for SoC Level Performance

DAC 2018 | Data Mining for SoC Level Performance

This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.

Demonstrating Functional Safety Compliance in Automotive IC Design

DAC 2018 | Demonstrating Functional Safety Compliance in Automotive IC Design

In this session, we will review some of the hurdles holding the industry back from conducting exhaustive fault campaigns and some innovative approaches to solving them. Also included is a review of acceleration strategies and best practices to enable them.

Emulation Platform Brings Unique Solutions to Automotive Market

DAC 2018 | Emulation Platform Brings Unique Solutions to Automotive Market

In this session we explore how the Veloce Emulation platform is positioned to deliver optimal verification solutions for the automotive market.

It’s Been 24 Hours - Should I Kill My Formal Run?

DAC 2018 | It’s Been 24 Hours – Should I Kill My Formal Run?

In this session we will show how to make an informed decision using “engine health” monitoring, a snapshot of the active logic being used by the analysis, and making an honest appraisal of the assumptions you applied at the beginning of the run.

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

DAC 2018 | No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

In this session we will share a real world case study of how the customer applied Questa CDC the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)

Portable Stimulus from IP to SoC - Achieve More Verification

DAC 2018 | Portable Stimulus from IP to SoC - Achieve More Verification

This session will show how Mentor’s inFact portable stimulus tool is applied across the verification spectrum and the spectrum of verification engines to achieve more verification with the same resources.

Portable Stimulus versus UVM: What's the Difference?

DAC 2018 | Portable Stimulus versus UVM: What's the Difference?

In this session, you will learn the differences between the Accellera Portable Test and Stimulus Standard (PSS) with the Universal Verification Methodology (UVM).

Portable Stimulus: A New Hope

DAC 2018 | Portable Stimulus: A New Hope

This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology.

Power Aware Simplifies Parametric PA-SIM Regression

DAC 2018 | Power Aware Simplifies Parametric PA-SIM Regression

In this session you will learn how Power Aware simulations play an important role in the System resources block verification.

Using Automation to Close the Loop Between Functional Requirements and their Verification

DAC 2018 | Using Automation to Close the Loop Between Functional Requirements and their Verification

This session will defined a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.

Using HLS to Accelerate Computer Vision for Autonomous Drive

DAC 2018 | Using HLS to Accelerate Computer Vision for Autonomous Drive

This session will introduce why HLS (High-level Synthesis) is such a good fit for computer vision and deep learning and how it can be used adapt rapidly changing algorithms and/or trained neural networks to low-power, high performance custom hardware accelerators.

UVM 1800.2 & The New and Improved UVM Cookbook

DAC 2018 | UVM 1800.2 & The New and Improved UVM Cookbook

This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard.

Validating Your SoC is True to Requirements

DAC 2018 | Validating Your SoC is True to Requirements

As challenging as verification is, validation is even more so. In this session, let’s explore how to validate all dimensions of functionality, performance, power and potentially for systems-on-chip.

Virtual Method Upcasting & Downcasting And Their Use In UVM

DAC 2018 | Virtual Method Upcasting & Downcasting And Their Use In UVM

In this session you will learn how upcasting and downcasting works and how they are frequently used in UVM testbench environments.

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