Released on March 17th, 2022.
Modern formal tools like Questa PropCheck automate the abstraction of many DUT elements; saving you setup time up-front, as well as wall clock run time and memory usage. But there are some circuit elements that the tools just can’t infer on their own from the raw RTL. Consequently, in this webinar we will give an overview of how to apply basic abstractions, how to set up & optimize constraints, and where and how to leverage Data Independence & Non-Determinism. All of these methods are easy-to-implement, and the resulting increase in formal analysis performance will be immediately apparent.
What You Will Learn:
- “Formal unfriendly” circuit designs that cannot be programmatically inferred from the raw RTL
- How to quickly and effectively apply these techniques (electronically, without editing your golden RTL source code)
Who Should Attend:
- Design & Verification engineers who are new to formal property checking