Released on April 6th, 2021.
In the beginning one created RTL and then wrote a testbench. In those simple days we could reach over to the DUT, create a clock in process, and implement our communication by toggling signals. Some of us still do this.
There is a better way. Proxy-driven testbenches allow us to create a reusable testbench that separates the pin wiggling from the test writing. This approach allows test writers to focus on finding ways to break a design rather than remembering protocol signals.
Even better, proxy-driven testbenches allow us to left-shift testbench development so that we can deliver a working testbench to our test writers before DUT coding ahs even begun.
In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.
What You Will Learn:
- The testbench software – proxy – RTL testbench structure
- How to write proxy-driven testbenches in SystemVerilog, VHDL, and Python