Modeling scenarios with the new Portable Test and Stimulus language (PSS) enables users to focus on the high-level requirements of what they need to test, and use automation to create specific valid tests and make those tests portable across a range of verification environments. Wouldn’t it be great if we could bring this same ability to focus on what we want to test instead of how to our existing SystemVerilog UVM testbench environments? We most certainly can by adding PSS-created tests to our UVM testbenches, but there’s an even easier way! inFact’s PSS Apps for SystemVerilog leverage the same core algorithms that enable PSS users to focus on what they want to test, not how. But, the inFact PSS Apps read in existing SystemVerilog classes and covergroups, allowing you to make the most of your existing testbench, while also increasing your verification productivity. Come see how the inFact PSS Apps can help you create correct-by-construction SystemVerilog covergroups, analyze your constraints pre-simulation, and generate efficient stimulus for coverage closure and bug hunting.
