Real Number Models (RNM) empowers verification engineer to describe an analog block as a discrete floating point model, and enable it to simulate in a digital solver at near-digital simulation speeds. In a design, when a RNM block interacts with a standard logic block, signal conversion happens and “real to logic” and “logic to real” boundary elements are inserted by digital solver. As the design hierarchy and complexity grows, the number of interaction increases and it becomes cumbersome to debug these boundary conversions. In this session we will dive into a simple scenario and demonstrate how you can take advantage of Symphony and the Visualizer Debug Environment to debug RNM boundary scenarios in case of a functional failure.
