Today's complex, multi-clock designs create challenges that must be addressed to avoid costly re-spins and long debug cycles. Design analysis and verification technologies that focus specifically on Clock-Domain Crossing (CDC) issues, using an integrated combination of verification technologies, have become a requirement. Design reviews and stringent methodologies are no longer enough. This session explains the importance of a complete CDC methodology to produce error-free silicon.
What You Will Learn
- The 3 common areas where CDC paths have functional errors
- How Questa CDC products can identify and eliminate all 3 common CDC error types
- Methods for effective CDC verification