Siemens EDA 2021 Functional Verification Webinar Series

CDC & RDC

Trouble: Three CDC Glitches That Only a Netlist Will See

This session will help you lower risks, development schedules and costs by identifying netlist CDC issues that are never caught with normal RTL CDC runs

A Methodology for Comprehensive CDC+RDC Analysis

This session will help you improve your development schedules and predictability by identifying the key functions and processes that must be deployed in a comprehensive CDC and RDC methodology.

Advance your Designs with Advances in CDC and RDC

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.

Formal Verification

Equivalence Checking for FPGA

In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

Formal 101 – Setting Up & Optimizing Constraints

In this session we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.

Formal 101 – Basic Abstraction Techniques

In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

The ABC of Formal Verification

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.

Functional Safety

Optimizing a Fault Campaign for Complex Mixed-Signal Devices

The primary objective of a fault campaign is to understand whether the safety architecture sufficiently prevents random failures from violating ISO 26262 safety requirements for both commercial and passenger automobiles. This session details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs.

Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

Achieving High Defect Coverage for Safety Critical and High Reliability Designs

In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets and helps accelerate product development to meet time-to-market pressures.

Simulation & Debug

Leveraging Advancements in UPF 3.1 for Effective Design and Verification

In this webinar, we shall explore some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

Low Power Considerations for Verification

Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.

I Didn’t Know Visualizer Could Do That

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Verification IP

Creating a Fast and Productive USB4 Verification Environment

This session walks through the step-by-step workflow to integrate Questa Verification IP (QVIP) – USB4 into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench.

A Guide to QVIP Workflow and Debug for PCIe

In this session, you will learn the step-by-step workflow to integrate Questa Verification IP (QVIP) - PCIe into a testbench including key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.

VIP Solutions for Protocol and Memory Verification

In this session, we'll provide the key attributes of the Verification IP and Memory Model products, and a high level summary of how they can be used to bring quality and time-to-market value to your project.

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