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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
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      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
      • Webinar Calendar

    • On-Demand Webinars

      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • All On-Demand Webinars

    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings

    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

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      • Mastering Questa
  • Home
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  • Siemens EDA 2021 Functional Verification Webinar Series

Siemens EDA 2021 Functional Verification Webinar Series

Now that we have fully transitioned from Mentor, a Siemens business to Siemens EDA, we are excited to keep you informed of the many great things we’ve been able to accomplish under our new name. We will be sharing short twice-weekly (Tuesdays and Thursdays at 8am PDT/11am EDT) webinar presentations with you over the coming months so that you can see what we’ve been up to. We’ve arranged these for you below according to areas of interest. We hope you enjoy these 30-minute sessions and find them informative.

Kurt Takara
Jin Hou
Vinayak Desai
Akshay Sarup
Ray Salemi
Lee Harrison
Rich Edelman
Joon Hong
Gordon Allan
Ashish Darbari

Upcoming Webinars

  • Low Power Considerations for Verification - Thursday, April 29th
  • Optimizing a Fault Campaign for Complex Mixed-Signal Devices - Tuesday, May 4th

Aero/Defense

Easy Test Writing with a Proxy-driven Testbench

Easy Test Writing with a Proxy-driven Testbench | Subject Matter Expert - Ray Salemi | Academy Live Web Seminar

In this session we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.

The Digital Twin: An Aerospace and Defense Revolution

The Digital Twin: An Aerospace and Defense Revolution | Subject Matter Expert - Ray Salemi | Academy Live Web Seminar

This session will provide a look into a seamless and comprehensive Digital Thread for Defense and the immense value it brings.

CDC & RDC

A Methodology for Comprehensive CDC+RDC Analysis

Formal 101 – Basic Abstraction Techniques | Subject Matter Expert - Kurt Takara | Siemens EDA 2021 Functional Verification Webinar Series

This session will help you improve your development schedules and predictability by identifying the key functions and processes that must be deployed in a comprehensive CDC and RDC methodology.

Advance your Designs with Advances in CDC and RDC

Advance your Designs with Advances in CDC and RDC | Subject Matter Expert - Kurt Takara | Academy Live Web Seminar

In this session you will gain an understanding of valuable new capabilities available in Questa CDC, RDC and Signoff CDC that are important to leverage early and often in development to ensure working and error-free multi-clock and reset designs.

Formal Verification

Formal 101 – Basic Abstraction Techniques

Formal 101 – Basic Abstraction Techniques | Subject Matter Expert - Jin Hou | Siemens EDA 2021 Functional Verification Webinar Series

In this session we will teach about the types of DUT constructs that commonly cause trouble for the formal analysis, and how to apply time-tested techniques to safely abstract them away so that the formal verification run can rapidly reach closure.

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself | Subject Matter Expert - Joon Hong | Academy Live Web Seminar

In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.

The ABC of Formal Verification

The ABC of Formal Verification Session | Dr. Ashish Darbari - Axiomise

This tutorial webinar covers formal methodology in detail focusing on the ABCs of formal: (A) abstraction, (B) bug hunting & building proofs, and (C) coverage in the context of property checking.

Functional Safety

Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

Exploration into Safety Analysis Techniques That Optimize the Safety Workflow | Subject Matter Expert - Ann Keffer | Siemens EDA 2021 Functional Verification Webinar Series

In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

Achieving High Defect Coverage for Safety Critical and High Reliability Designs

Achieving High Defect Coverage for Safety Critical and High Reliability Designs | Subject Matter Expert - Lee Harrison | Academy Live Web Seminar

In this session you will gain an understanding of how Siemens EDA provides practices, methodologies and integrated tool flows that provides a path to reaching the required manufacturing test quality needed for designs targeted at critically safe and high reliability markets and helps accelerate product development to meet time-to-market pressures.

Verification IP

A Guide to QVIP Workflow and Debug for PCIe

A Guide to QVIP Workflow and Debug for PCIe | Subject Matter Expert - Akshay Sarup | Siemens EDA 2021 Functional Verification Webinar Series

In this session, you will learn the step-by-step workflow to integrate Questa Verification IP (QVIP) - PCIe into a testbench including key strides which dramatically reduces the integration efforts from weeks down to few hours allowing Verification Engineers to be more productive during their verification cycle.

VIP Solutions for Protocol and Memory Verification

VIP Solutions for Protocol and Memory Verification | Subject Matter Expert - Gordon Allan | Academy Live Web Seminar

In this session, we'll provide the key attributes of the Verification IP and Memory Model products, and a high level summary of how they can be used to bring quality and time-to-market value to your project.

Visualizer Debug

I Didn’t Know Visualizer Could Do That

I Didn’t Know Visualizer Could Do That Session | Rich Edelman

In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

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