Design verification methodologies are in an endless race to catch up with exploding verification needs. As soon as the verification industry standardizes on a methodology, a new set of requirements emerges. While methodologies like coverage-driven test ranking and sophisticated checkers can help focus the verification results on the most high-value data points, a real live person must still sift through all of the output and navigate the failure analysis–bug identification–fix–validate cycle. The debug challenge is big and is only growing.
Indeed, based on semi-annual customer surveys debug is now exceeding 39% of an engineer’s time, which is more than any other single verification task. Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and simultaneously meet quality goals. Join us for this comprehensive seminar to learn the very latest verification techniques.
