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Relieving the Parameterized Coverage Headache

Article - Jun 15, 2012 by Bryan Ramirez

Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage data is documented for designs operating in a single configuration. However, complications arise when parameters are introduced into the design, especially when creating customizable IP. This article discusses the coverage-related pitfalls and solutions when dealing with parameterized designs.
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs

Article - Jun 15, 2012 by Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks

Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.
Better Living Through Better Class-Based SystemVerilog Debug

Article - Jun 15, 2012 by Rich Edelman

SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
Verification Horizons - Volume 8, Issue 2

Resource (Verification Horizons Archive) - Jun 15, 2012 by Tom Fitzpatrick

"On a recent visit to the Evergreen Aviation & Space Museum in Oregon, I had an opportunity to see some great examples of what, for their time, were incredibly complex pieces of engineering... those successes were the result of early failures where engineers learned the hard way...”
Introduction to Metrics

Session - Jun 01, 2012 by Harry Foster

This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
The Driving Forces for Change

Session - Jun 01, 2012 by Andreas Meyer

This session examines the issues that are motivating change and the need for metrics-driven processes and discusses what is not working in today’s IP-based SoC design flows.
What Can Metrics Tell Us?

Session - Jun 01, 2012 by Andreas Meyer

This session expands our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
What's Needed to Address the Problem?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses four important aspects of a successful metrics-driven process: understanding the landscape, categorization, run-time control and reporting.
What's Needed to Adopt Metrics?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses important aspects of an implementation that should be considered when architecting a solution.
Evolving Trends in Functional Verification

Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster

2012 Wilson Research Group Functional Verification Study Results
What to Expect After Adopting the Metrics

Session - Jun 01, 2012 by Andreas Meyer

This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
Metrics in SoC Verification

Track - Jun 01, 2012 by Andreas Meyer

In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
Introduction to UVM Connect

Session - May 31, 2012 by Adam Erickson

This session introduces UVM Connect and explains the benefits of adoption. It also reviews the principles and concepts behind the TLM1 and TLM2 standards and reviews the basic connection syntax and semantics of both SystemVerilog and SystemC.
Introduction to UVM Connect

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
Connections

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
Connections

Session - May 31, 2012 by Adam Erickson

This session shows how to establish TLM-based connections between components in SystemVerilog and SystemC.
Converters

Session - May 31, 2012 by Adam Erickson

This session shows how to write the converters that are needed to transfer transaction data across the language boundary.
Converters

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
UVM Command API

Session - May 31, 2012 by Adam Erickson

This session shows how to access and control key aspects of UVM simulation from SystemC.
UVM Command API

Resource (Slides (.PDF)) - May 31, 2012 by Adam Erickson
UVM Connect User Guide

Resource (Reference Documentation) - May 31, 2012 by Adam Erickson
UVM 1.1b Class Reference

Resource (Reference Documentation) - May 21, 2012 by

v1.1b The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
UVM Connect 2.1.4 Kit

Resource (Tarball) - Feb 20, 2012 by John Stickley
Verification Horizons - Volume 8, Issue 1

Resource (Verification Horizons Archive) - Feb 01, 2012 by Tom Fitzpatrick

"Our kitchen renovation is nearly complete... Just as with verification, the key is to have a plan... take as many contingencies into account as you can... and... be able to handle constrained random stimulus.”
UVM 1.1a Class Reference

Resource (Reference Documentation) - Dec 01, 2011 by

v1.1a The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.