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Using Formal Analysis to Block and Tackle

Article - Feb 25, 2013 by Paul B. Egan - Rockwell Automation

This article will explain how we applied formal analysis at the block level, extended this to full chip and describe how we significantly reduced verification time at both the block and chip level. Just like a block and tackle provides a mechanical advantage, the formal connectivity flow provides a verification advantage
Bringing Verification and Validation under One Umbrella

Article - Feb 25, 2013 by Hans Van Der Schoot

The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
System Level Code Coverage using Vista Architect and SystemC

Article - Feb 25, 2013 by Ken P. McCarty - Siemens EDA

SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.
The Evolution of UPF: What’s Next?

Article - Feb 25, 2013 by Erich Marschner

Usage of the Unified Power Format (UPF) is growing rapidly as low power design and verification becomes increasingly necessary. In parallel, the UPF standard has continued to evolve. A previous article1 described and compared the initial UPF standard, defined by Accellera, and the more recent IEEE 1801-2009 UPF standard, also known as UPF 2.0. The IEEE definition of UPF is the current version of the standard, at least for now, but that is about to change.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

Article - Feb 25, 2013 by Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.

SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
SVA in a UVM Class-based Environment

Article - Feb 25, 2013 by Ben Cohen

This article demonstrates how SVA complements a UVM class-based environment. It also demonstrates how the UVM severity levels can be used in all SVA action blocks instead of the SystemVerilog native severity levels.
The Formal Verification of Design Constraints

Article - Feb 25, 2013 by Ajay Daga - FishTail Design Automation

There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation.
OVM to UVM Migration, or There and Back Again: A Consultant’s Tale

Article - Feb 25, 2013 by Mark Litterick - Verilab GmbH

This article presents an interesting OVM to UVM migration story where we successfully translated a whole family of verification components from OVM 2.1.2 to UVM, assessed the impact, and then reworked the original OVM code, which was still live in a series of ongoing derivative projects, to make the ongoing translations totally automatic and part of the project release mechanism.
Verification Horizons - Volume 9, Issue 1

Resource (Verification Horizons Archive) - Feb 01, 2013 by Tom Fitzpatrick

"As verification engineers, we have to be able to forecast the accurate completion of our projects and also be able to cope with problems that may occur. Unfortunately, there are severe consequences when we get it wrong.”
VHDL-2008 Overview

Session - Jan 18, 2013 by Jim Lewis

This session is a brief overview of all the VHDL 2008 improvements.
Testbench Enhancements

Session - Jan 18, 2013 by Jim Lewis

Through extended and new capability, VHDL 2008 enables the creation of advanced verification environments. This session examines these changes and the value they deliver.
RTL Enhancements

Session - Jan 18, 2013 by Jim Lewis

VHDL 2008 enhancements simplify RTL coding. Among these changes are simplified sensitivity lists, simplified conditionals (if statements), and simplified case statements. This session examines these changes and the value they deliver.
Operator Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session will discuss the value of the many new enhancements to the VHDL 2008 operators including Unary reduction, Array operations and mods for physical time.
Package Type Enhancements

Session - Jan 18, 2013 by Jim Lewis

VHDL 2008 includes numerous tune ups to the packages and how the packages are integrated into the language. The session explores the new packages and modifications to the packages as well as the value these updates deliver.
Fixed Point Package

Session - Jan 18, 2013 by Jim Lewis

The new package, fixed_generic_pkg, defines fixed point math types and operations. This session will explain the details of the new package.
Floating Point Package

Session - Jan 18, 2013 by Jim Lewis

The new package, float_generic_pkg, defines floating point math types and operations. This session will explain the details of the new package.
VHDL 2008: Why It Matters

Track - Jan 17, 2013 by Jim Lewis

VHDL 2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed- and floating-point math packages. VHDL 2008 is the largest change to VHDL since 1993; this track is designed to explain the value of the new VHDL 2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.
Improve AMS Verification Quality

Track - Dec 01, 2012 by Ahmed Eisawy

This track introduces methodologies available in AMS design environments that could help quantify the quality of the Analog/Mixed-Signal (AMS) verification process. Understanding these approaches, will help learn how to properly address the various issues and problems in AMS verification process, thus, help improve the overall process Quality.
Overview to Improve AMS Quality

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces the challenges in improving mixed-signal verification quality. A high-level description of the various aspects affecting the overall quality of a mixed-signal design is introduced.
Analog Aspects in AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session covers the main aspects that affect the quality of an analog design and introduces the possible means to address those areas efficiently to help improve the quality of an analog design, while being integrated in the overall AMS design.
Extend Power Aware Verification to AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces the concept of power aware verification, why it’s needed in a Digital domain and how it can be used in an AMS design. Mixed-signal power aware verification is further described to show the benefits from such flow to the overall quality of AMS design and verification.
Extend Structured Formal Verification to AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session defines the necessary extensions to the digital structured formal verification to the mixed-signal environment. Extending the structured formal verification to the mixed-signal domain is about covering how to write mixed-signal properties to the same database used in the digital domain for proper coverage management and thus, improve the overall quality.
Questa ADMS: AMS Quality

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces Questa ADMS, and how it can be adapted in existing design flows supporting available methodologies with little or no impact on the design flow, supporting virtually all language standards with a variety of features and capabilities to help improve the overall quality of a mixed-signal design and verification to reach the goal of successful first tape-out using reasonable resources.
Effectively Modeling and Analyzing Coverage

Webinar - Nov 15, 2012 by Tom Fitzpatrick

In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.
ST-Ericsson Speeds Time to Functional Verification Closure with Questa

Article - Oct 01, 2012 by Rachida El IDRISSI - ST-Ericsson

Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.