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Evolution of UPF: Getting Better All the Time

Article - Oct 01, 2012 by Erich Marschner

This article gives a high-level overview of the concepts and capabilities that UPF provides and how those concepts and capabilities have evolved over the past few years. It also gives a preview of what is coming in the next version of UPF.
Improving Analog/Mixed-Signal Verification Productivity

Article - Oct 01, 2012 by Ahmed Eisawy

Nearly all of today's chips contain Analog/Mixed-Signal circuits. Although these often constitute only 25% of the total die, they may be 100% of the product differentiation and also, unfortunately, 80% of the problems in actually getting the chip to market in a cost effective and timely way.
VHDL-2008: Why It Matters

Article - Oct 01, 2012 by Jim Lewis

This article overviews the changes and the value they bring to your design process. Topics are categorized into three major sections: testbench, RTL, and packages/operators.
Verification Horizons - Volume 8, Issue 3

Resource (Verification Horizons Archive) - Oct 01, 2012 by Tom Fitzpatrick

"For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible.”
UVM 1.1c Class Reference

Resource (Reference Documentation) - Sep 19, 2012 by

v1.1c The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
More UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to implement registers and score-boarding at the register layer.
Protocol Layering

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
Introduction to UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.
C-Based Stimulus for UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn more about a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents.
UVM Debug

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this Verification Cookbook session, you will learn how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
Scoreboards and Results Predictors in UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
OVM to UVM Migration

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session you will be introduced to a step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.
Customization in UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT and how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
Improving FPGA Debugging with Assertions

Article - Sep 10, 2012 by Harry Foster

Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.
UVM Connect 2.2 Kit

Resource (Tarball) - Sep 07, 2012 by John Stickley
FPGA Verification Capabilities

Track - Aug 30, 2012 by Ray Salemi

This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
Introduction from Harry Foster

Session - Aug 30, 2012 by Harry Foster

This session is an introduction to various code coverage metrics and how to apply them.
Overview and Welcome

Session - Aug 30, 2012 by Ray Salemi

This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
Code Coverage

Session - Aug 30, 2012 by Ray Salemi

This session is an introduction to various code coverage metrics and how to apply them.
Test Planning

Session - Aug 30, 2012 by Ray Salemi

This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
Applied Assertions

Session - Aug 30, 2012 by Ray Salemi

This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
Transactions

Session - Aug 30, 2012 by Ray Salemi

This session shows you how to create a transaction level test bench using modules instead of object.
Self-Checking Testbenches

Session - Aug 30, 2012 by Ray Salemi

This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
Automatic Stimulus

Session - Aug 30, 2012 by Ray Salemi

This session introduces constrained-random stimulus for automatic stimulus generation.
Functional Coverage

Session - Aug 30, 2012 by Ray Salemi

This session shows you how to implement functional coverage using SystemVerilog covergroups.