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Introduction to Functional Verification
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
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Understanding the Two Main Testing Approaches
Lesson - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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Understanding the Two Main Testing Approaches
Resource (Slides (.PDF)) - Jan 10, 2025 by Harry Foster
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
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What is a Reusable Testbench?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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What is a Reusable Testbench?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
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How Can I Reuse Testbench Components?
Lesson - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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How Can I Reuse Testbench Components?
Resource (Slides (.PDF)) - Jan 10, 2025 by Tom Fitzpatrick
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
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UVM Test Flow
Lesson - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
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UVM Test Flow
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
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Creating and Using a Test Plan
Session - Jan 10, 2025 by Bob Oden
This session, with two lessons shown in the tabs below, covers the purpose and content sources of a test plan. Learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps. By the end, you’ll understand how to effectively create and utilize a test plan for comprehensive verification.
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Creating a Test Plan
Lesson - Jan 10, 2025 by Bob Oden
You will learn the purpose and content sources of a test plan in this important lesson.
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Creating a Test Plan
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn the purpose and content sources of a test plan in this important lesson.
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Test Plan Fields
Lesson - Jan 10, 2025 by Bob Oden
You will learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps.
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Test Plan Fields
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps.
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Data Types and Procedural Statements
Session - Jan 10, 2025 by Bob Oden
This session, with four lessons shown in the tabs below, covers SystemVerilog’s default data types, variable declaration, and type casting. Learn about the two basic array types, their usage, and indexing. Explore the array types available and the methods for their use. Understand selection, loop, and jump statements in SystemVerilog. By the end, you’ll have a solid grasp of these fundamental concepts.
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SystemVerilog Data Types
Lesson - Jan 10, 2025 by Bob Oden
You will learn SystemVerilog's default data types, variable declaration, and type casting in this informative session.
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SystemVerilog Data Types
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn SystemVerilog's default data types, variable declaration, and type casting in this informative session.
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Multidimensional Arrays
Lesson - Jan 10, 2025 by Bob Oden
You will learn the two basic array types in SystemVerilog and learn their usage and indexing in this lesson.
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Multidimensional Arrays
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn the two basic array types in SystemVerilog and learn their usage and indexing in this lesson.
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Built-In Unpacked Arrays
Lesson - Jan 10, 2025 by Bob Oden
You will learn the array types available in SystemVerilog and the methods provided for their use in this session.
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Built-In Unpacked Arrays
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn the array types available in SystemVerilog and the methods provided for their use in this session.
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Procedural Programming Statements
Lesson - Jan 10, 2025 by Bob Oden
You will learn about selection, loop, and jump statements in SystemVerilog in this insightful lesson.
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Procedural Programming Statements
Resource (Slides (.PDF)) - Jan 10, 2025 by Bob Oden
You will learn about selection, loop, and jump statements in SystemVerilog in this insightful lesson.
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Creating and Using Functional Coverage
Session - Jan 10, 2025 by Harry Foster
This session, with four lessons shown in the tabs below, covers verification metrics and coverage classifications to determine what’s verified, what’s not, and when we’re done. Learn about SystemVerilog constructs for creating a functional coverage model and recording coverage data. Explore creating reusable covergroups, covergroup methods, extracting coverage results, and controlling SystemVerilog cover capabilities. Understand how to sample covergroups and where to add them in your testbench.
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Introduction to Functional Coverage
Lesson - Jan 10, 2025 by Harry Foster
You will learn verification metrics and coverage classifications to determine what’s verified, what’s not, and when we’re done.