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Code Coverage
Session - Aug 30, 2012 by Ray Salemi
This session is an introduction to various code coverage metrics and how to apply them.
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Test Planning
Session - Aug 30, 2012 by Ray Salemi
This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
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Applied Assertions
Session - Aug 30, 2012 by Ray Salemi
This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
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Transactions
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to create a transaction level test bench using modules instead of object.
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Self-Checking Testbenches
Session - Aug 30, 2012 by Ray Salemi
This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
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Automatic Stimulus
Session - Aug 30, 2012 by Ray Salemi
This session introduces constrained-random stimulus for automatic stimulus generation.
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Functional Coverage
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to implement functional coverage using SystemVerilog covergroups.
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Using the UVM Register Layer
Resource (Slides (.PDF)) - Jun 22, 2012 by John Aynsley
Slides from DAC 2012 where John Anysley from Doulos shares the Architecture of the Register Layer, The Register Model and Running Register Sequences.
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Siemens EDA has Accellera's Latest Standard Covered
Article - Jun 15, 2012 by Darron May
If you can't measure something, you can't improve it. For years, verification engineers have used "coverage" as a way to measure completeness of the verification effort. Of course, there are many types of coverage, from different types of code coverage to functional coverage, as well as many tools, both dynamic and static, that provide coverage information.
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Is Intelligent Testbench Automation For You?
Article - Jun 15, 2012 by Mark Olen
Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.
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Automated Generation of Functional Coverage Metrics for Input Stimulus
Article - Jun 15, 2012 by Mike Andrews - Siemens EDA
Questa inFact allows for graphical definition of the coverage goals and can, with the 10.1 release, automatically generate SystemVerilog covergroups from this definition, including the exclusions needed to accurately represent the achievable coverage. This article describes how this capability can simplify the definition of more comprehensive stimulus coverage metrics.
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Targeting Internal-State Scenarios in an Uncertain World
Article - Jun 15, 2012 by Matthew Ballance
The challenges inherent in verifying today's complex designs are widely understood. Just identifying and exercising all the operating modes of one of today's complex designs can be challenging. Creating tests that will exercise all these input cases is, challenging and labor-intensive. Using directed-test methodology, is challenging to create sufficiently-comprehensive tests to ensure design quality, due to the amount of engineering effort needed to design, implement, and manage the test suite.
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Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Article - Jun 15, 2012 by Jim Kenney - Siemens EDA
With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware. Emulation has the speed and capacity to do this before the investment is made in prototypes or silicon.
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On the Fly Reset
Article - Jun 15, 2012 by Mark Peryer
A common verification requirement is to reset a design part of the way through a simulation to check that it will come out of reset correctly and that any non-volatile settings survive the process. Almost all testbenches are designed to go through some form of reset and initialization process at their beginning, but applying reset at a mid-point in the simulation can be problematic.
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Relieving the Parameterized Coverage Headache
Article - Jun 15, 2012 by Byran Ramirez
Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage data is documented for designs operating in a single configuration. However, complications arise when parameters are introduced into the design, especially when creating customizable IP. This article discusses the coverage-related pitfalls and solutions when dealing with parameterized designs.
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Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
Article - Jun 15, 2012 by Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks
Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.
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Better Living Through Better Class-Based SystemVerilog Debug
Article - Jun 15, 2012 by Rich Edelman
SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
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Introduction to Metrics
Session - Jun 01, 2012 by Harry Foster
This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
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The Driving Forces for Change
Session - Jun 01, 2012 by Andreas Meyer
This session examines the issues that are motivating change and the need for metrics-driven processes.
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What Can Metrics Tell Us?
Session - Jun 01, 2012 by Andreas Meyer
This session expand our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
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What's Needed to Address the Problem?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses four important aspects of a successful metrics-driven process.
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What's Needed to Adopt Metrics?
Session - Jun 01, 2012 by Andreas Meyer
This session discusses important aspects of an implementation that should be considered when architecting a solution.
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Evolving Trends in Functional Verification
Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster
2012 Wilson Research Group Functional Verification Study Results
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What to Expect After Adopting the Metrics
Session - Jun 01, 2012 by Andreas Meyer
This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
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Metrics in SoC Verification
Track - Jun 01, 2012 by Andreas Meyer
In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.