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Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

Resource (Paper (.PDF)) - Feb 27, 2013 by Mike Horn

With parameterized agents, driver level data rate controls and timing controls in addition to utilizing the broad capabilities of OVM and UVM, the GOES-R C&DH team produced FPGAs that performed admirably in the lab.
Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

Paper - Feb 27, 2013 by Mike Horn

In 2010–2011, Lockheed Martin Space Systems designed and verified eight FPGAs for the Command and Data Handling (C&DH) subsystem of the NOAA/NASA Geostationary Operational Environmental Satellite R-Series (GOES-R), scheduled to launch in 2015. Hardware validation and integration of these FPGAs went smoothly. Perhaps the best measure of the success: the FPGAs performed with almost no functional failures during integration and test.
Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

Resource (Recording) - Feb 27, 2013 by Adam Erickson

UVM Connect bridges the SystemC and SystemVerilog language boundary to provide seamless TLM1 and TLM2 connectivity between components residing in those two languages.
Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

Paper - Feb 27, 2013 by Adam Erickson

This paper describes the purpose, requirements, development challenges, and applications of an open-source library for establishing standard TLM-based communication between SystemC (SC) and SystemVerilog (SV) models, including C/C++ models wrapped in SC or SV. It also describes a SystemC-side interface for controlling simulations based on the UVM in SystemVerilog. The UVM Connect library is available for download and has been proven to work on three major EDA vendors’ simulators. 1
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Resource (Paper (.PDF)) - Feb 26, 2013 by Mark Peryer

This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Paper - Feb 26, 2013 by Mark Peryer

On-chip bus interconnect fabrics have become critical sub-systems in SoC platforms. Not only do they need to be functionally correct, but they also need to deliver the performance demanded by user applications. This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
Seven Separate Sequence Styles Speed Stimulus Scenarios

Resource (Paper (.PDF)) - Feb 26, 2013 by Mark Peryer

This paper describes seven common sequence design patterns which should prove useful to all UVM sequence writers. These patterns can be used stand-alone or combined to solve practical stimulus generation problems using UVM sequences.
Sequence, Sequence on the Wall: Who's the Fairest of Them All?

Paper - Feb 26, 2013 by Rich Edelman

The reader of this paper is interested to use UVM sequences to achieve his test writing goals. Examples of UVM sequences will be used to demonstrate basic and advanced techniques for creating interesting, reusable sequences and tests.
Seven Separate Sequence Styles Speed Stimulus Scenarios

Paper - Feb 26, 2013 by Mark Peryer

Writing effective stimulus in UVM can prove to be challenging for various reasons, but not knowing about the relevant coding design patterns should not be one of them. There are various alternative techniques for writing sequences and choosing the right approach requires mastery of several styles. This paper describes seven common sequence design patterns which should prove useful to all UVM sequence writers.
Boosting Simulation Performance of UVM Registers in High Performance Systems

Resource (Paper (.PDF)) - Feb 26, 2013 by Ahmed Yehia - Siemens EDA

In the paper, we give a quick overview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks, showing the simulation performance bottlenecks observed when performing on high-speed buses.
Boosting Simulation Performance of UVM Registers in High Performance Systems

Paper - Feb 26, 2013 by Ahmed Yehia - Siemens EDA

In the paper, we give a quick overview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks, showing the simulation performance bottlenecks observed when performing on high-speed buses. We then present an efficient overlay layer that can be easily integrated on top of the UVM register library, making the library suitable for high as well as low performance systems.
Monitors, Monitors Everywhere: Who Is Monitoring the Monitors

Resource (Paper (.PDF)) - Feb 26, 2013 by Rich Edelman

In a verification environment the task of a monitor is to monitor activity on a set of DUT pins. This could be as simple as looking at READ/WRITE pins or as complex as a complete protocol bus, such as AXI or PCIe. In a very simple case a monitor can be looking at a pin or a set of pins and generating an event or raising a flag every time there is a change in signal values. The flag or event can trigger a scoreboard or coverage collector to perform an activity.
Monitors, Monitors Everywhere: Who Is Monitoring the Monitors

Paper - Feb 26, 2013 by Rich Edelman

The reader of this paper should be interested in predicting the behavior of his hardware or is interested in monitoring his hardware. This paper will review phase-level monitoring, transaction-level monitoring, and general monitoring. In-order and out-of-order transaction-level monitors and UVM constructs for single and multiple port monitors will be demonstrated, including discussion about simple function implementations versus FIFO and threaded implementations.
Using Formal Analysis to Block and Tackle

Article - Feb 25, 2013 by Paul B. Egan - Rockwell Automation

This article will explain how we applied formal analysis at the block level, extended this to full chip and describe how we significantly reduced verification time at both the block and chip level. Just like a block and tackle provides a mechanical advantage, the formal connectivity flow provides a verification advantage
Bringing Verification and Validation under One Umbrella

Article - Feb 25, 2013 by Hans Van Der Schoot

The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
System Level Code Coverage using Vista Architect and SystemC

Article - Feb 25, 2013 by Ken P. McCarty - Siemens EDA

SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.
The Evolution of UPF: What’s Next?

Article - Feb 25, 2013 by Erich Marschner

Usage of the Unified Power Format (UPF) is growing rapidly as low power design and verification becomes increasingly necessary. In parallel, the UPF standard has continued to evolve. A previous article1 described and compared the initial UPF standard, defined by Accellera, and the more recent IEEE 1801-2009 UPF standard, also known as UPF 2.0. The IEEE definition of UPF is the current version of the standard, at least for now, but that is about to change.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

Article - Feb 25, 2013 by Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.

SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
SVA in a UVM Class-based Environment

Article - Feb 25, 2013 by Ben Cohen

This article demonstrates how SVA complements a UVM class-based environment. It also demonstrates how the UVM severity levels can be used in all SVA action blocks instead of the SystemVerilog native severity levels.
The Formal Verification of Design Constraints

Article - Feb 25, 2013 by Ajay Daga - FishTail Design Automation

There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation.
OVM to UVM Migration, or There and Back Again: A Consultant’s Tale

Article - Feb 25, 2013 by Mark Litterick - Verilab GmbH

This article presents an interesting OVM to UVM migration story where we successfully translated a whole family of verification components from OVM 2.1.2 to UVM, assessed the impact, and then reworked the original OVM code, which was still live in a series of ongoing derivative projects, to make the ongoing translations totally automatic and part of the project release mechanism.
Verification Horizons - Volume 9, Issue 1

Resource (Verification Horizons Archive) - Feb 01, 2013 by Tom Fitzpatrick

"As verification engineers, we have to be able to forecast the accurate completion of our projects and also be able to cope with problems that may occur. Unfortunately, there are severe consequences when we get it wrong.”
Improve AMS Verification Quality

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool can be adapted in existing design flows supporting the available methodologies with little or no impact on the design flow.
Extend Structured Formal Verification to AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This sessions defines the necessary extensions to the Digital Structured Formal Verification to the Mixed-Signal environment.
Extend Power-Aware Verification to AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the concept of Power-Aware verification, why it’s needed in a Digital domain and how it can be used in an AMS design.