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New School Coverage Closure

Webinar - May 29, 2015 by Mark Eslinger

In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.
UVMC 2.3.1 Library

Resource (Reference Documentation) - May 15, 2015 by John Stickley

The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Technical Paper - SVA Local Variable Coding Guidelines for Efficient Use

Resource - May 15, 2015 by
Questa Simulation: Power Aware

Demo - May 12, 2015 by Chuck Seeley

In this demo, you will learn the UPF based Power Aware features available in Questa PASim.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - May 11, 2015 by Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on the effectiveness of verification in terms of FPGA project schedule and bug escapes. In this blog, I present verification techniques and technologies adoption trends, as identified by the 2014 Wilson Research Group study.
FPGA Functional Verification Study - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the FPGA verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
IC/ASIC Functional Verification Study - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the IC/ASIC verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
Part 4: FPGA Verification Effectiveness Trends

Resource (Verification Horizons Blog) - Apr 21, 2015 by Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on the amount of effort spent in FPGA verification. We have seen in previous blogs that a significant amount of effort is being applied to FPGA functional verification. In this blog I focus on the effectiveness of verification in terms of FPGA project schedule and bug escapes.
Part 3: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Apr 01, 2015 by Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on the controversial topic of effort spent in FPGA verification. This blog continues that discussion. I stated in my previous blog that I don’t believe there is a simple answer to the question, “how much effort was spent on verification in your last FPGA project?”
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Slides (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Paper (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Conference - Mar 31, 2015 by Tom Fitzpatrick

This session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly and become productive with using UVM for the verification of most types and sizes of digital designs modeled in VHDL, Verilog or SystemVerilog. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.
UVMC 2.3.0 Library

Resource (Reference Documentation) - Mar 15, 2015 by

v2.3.0 The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

Resource (Paper (.PDF)) - Mar 15, 2015 by Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. LSI, Samsung Electronics Co. Ltd.

In this paper, you learn the need for handling CDCs as part of sequential clock gating. A new approach was presented where CDCs were natively modeled as a cost function in the power optimization objective.
Samsung: Clock-Domain Crossing Aware Sequential Clock Gating

Paper - Mar 15, 2015 by Jianfeng Liu, Mi-Suk Hong, Kyungtae Do, Jung Yun Choi, Jaehong Park S. LSI, Samsung Electronics Co. Ltd.

In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.
Part 2: FPGA Verification Effort Trends

Resource (Verification Horizons Blog) - Mar 11, 2015 by Harry Foster

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study ( click here ). In my previous blog , I focused on FPGA design trends. In this blog, I present findings from our study related to the effort spent in verification. Directly asking study participants how much effort they spend in verification will not work.
Does Design Size Influence First Silicon Success?

Article - Mar 11, 2015 by Harry Foster

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification at that point in time. However, after the 2004 study, no additional Collett studies were conducted, which left a void in identifying industry trends.
Successive Refinement: A Methodology for Incremental Specification of Power Intent

Article - Mar 11, 2015 by Adnan Khan, John Biggs & Eamonn Quigley - Arm

In this article, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system. We explain how a system’s power management architecture can be specified in a technology-independent manner and verified abstractly, before implementation. We also explain how implementation information can be added later.
Power Aware RTL Verification of USB 3.0 IPs

Article - Mar 11, 2015 by Gayathri SN, Badrinath Ramachandra - L&T Technology Services Limited

This article describes a specific Power Management scheme used in a USB 3.0 Device IP controller. It also describes how Questa Power Aware helped IP designers realize reliable, accurate and scalable low power architectures and comprehensive verification of these architectures. Additionally, this also shares the experience in using the UPF to define various power domains, isolation strategies and methods to control power states from the testbench.
Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 by Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Small, Maintainable Tests

Article - Mar 11, 2015 by Ashley Winn - Sondrel IC Design Services

In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested.
Functional Coverage Development Tips: Do’s and Don'ts

Article - Mar 11, 2015 by Samrat Patel, Vipul Patel - eInfochips

The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort.
UVM Connect 2.3.0 Kit

Resource (Tarball) - Mar 10, 2015 by John Stickley
UVM Connect 2.3.0 Primer

Resource (Reference Documentation) - Mar 10, 2015 by John Stickley