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Basic Formal Closure, (Black Boxing and Cutpoint)

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger
Basic Formal Closure (Black Boxing and Cutpoint)

Session - Jun 05, 2015 by Mark Eslinger

At some point formal engines will begin to struggle under the weight of the state space. This session will show two simple techniques to safely limit the states the engines need to process, enabling more in-depth results.
Formal Model Checking

Resource (Slides (.PDF)) - Jun 05, 2015 by Mark Eslinger
Questa PropCheck

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo the Questa PropCheck tool and will review features including the details window, properties window, along with source, waveform and schematic debug features.
SecureCheck: How Secure is your Design?

Session - Jun 05, 2015 by Mark Eslinger

This session will show how to exhaustively prove the integrity of the hardware root of trust with your RTL and a clear text, human and machine readable spreadsheet to specify the critical storage and allowed access paths.
Questa SecureCheck

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo the Questa SecureCheck tool and will review features including the details window, properties tab, waveform and schematic views.
Mitigating X Effects in Your Verification

Session - Jun 05, 2015 by Mark Eslinger

In this session we’ll take a quick look at the various types of X effects and how they can impact your design. We’ll also look at some common sources of X which are the originators of these effects.
Questa X-Check: Finding X-Corruption

Demo - Jun 05, 2015 by Mark Eslinger

This session will demo finding X corruption in your design using Questa X-Check.
UVM Debug? Beyond Logfiles

Session - Jun 01, 2015 by Rich Edelman

In this session you will learn about tips and tricks to move beyond logfiles, towards better UVM Debug.
UVM Debug? Beyond Logfiles

Resource (Slides (.PDF)) - Jun 01, 2015 by Rich Edelman

In this session you will learn about tips and tricks to move beyond logfiles, towards better UVM Debug.
New School Coverage Closure

Webinar - May 29, 2015 by Mark Eslinger

In this session, you will learn a new school formal verification method which automates the job of focusing coverage closure efforts.
UVMC 2.3.1 Library

Resource (Reference Documentation) - May 15, 2015 by John Stickley

The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Technical Paper - SVA Local Variable Coding Guidelines for Efficient Use

Resource - May 15, 2015 by
Questa Simulation: Power Aware

Demo - May 12, 2015 by Chuck Seeley

In this demo, you will learn the UPF based Power Aware features available in Questa PASim.
FPGA Trends in Functional Verification - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the FPGA verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
ASIC/IC Trends in Functional Verification - 2014

Session - May 08, 2015 by Harry Foster

Harry Foster discusses the IC/ASIC verification trends from the 2014 Wilson Research Group Functional Verification Study, and provides some insight into its findings.
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Slides (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Resource (Paper (.PDF)) - Mar 31, 2015 by Tom Fitzpatrick
UVM Rapid Adoption: A Practical Subset of UVM

Conference - Mar 31, 2015 by Tom Fitzpatrick

This session focusses on defining a subset of the UVM base classes, methods, and macros that will enable engineers to learn UVM more quickly and become productive with using UVM for the verification of most types and sizes of digital designs modeled in VHDL, Verilog or SystemVerilog. You might be surprised at just how small of a subset of UVM is really needed in order to verify complex designs effectively with UVM.
UVMC 2.3.0 Library

Resource (Reference Documentation) - Mar 15, 2015 by

v2.3.0 The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
Does Design Size Influence First Silicon Success?

Article - Mar 11, 2015 by Harry Foster

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification at that point in time. However, after the 2004 study, no additional Collett studies were conducted, which left a void in identifying industry trends.
Successive Refinement: A Methodology for Incremental Specification of Power Intent

Article - Mar 11, 2015 by Adnan Khan, John Biggs & Eamonn Quigley - Arm

In this article, we present the UPF Successive Refinement methodology in detail. We explain how power management constraints can be specified for IP blocks to ensure correct usage in a power-managed system. We explain how a system’s power management architecture can be specified in a technology-independent manner and verified abstractly, before implementation. We also explain how implementation information can be added later.
Power Aware RTL Verification of USB 3.0 IPs

Article - Mar 11, 2015 by Gayathri SN, Badrinath Ramachandra - L&T Technology Services Limited

This article describes a specific Power Management scheme used in a USB 3.0 Device IP controller. It also describes how Questa Power Aware helped IP designers realize reliable, accurate and scalable low power architectures and comprehensive verification of these architectures. Additionally, this also shares the experience in using the UPF to define various power domains, isolation strategies and methods to control power states from the testbench.
Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 by Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.