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The Verification Academy Patterns Library

Article - Mar 02, 2016 by Harry Foster

The literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions. For example, the UVM Cookbook (available out on the Verification Academy) references the observe pattern when discussing the Analysis Port .
Increased Efficiency with Questa VRM and Jenkins Continuous Integration

Article - Mar 02, 2016 by Thomas Ellis

For all the incredible technological advances to date, no one has found a way to generate additional time. Consequently, there never seems to be enough of it. Since time cannot be created, it is utterly important to ensure that it is spent as wisely as possible.
Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution

Article - Mar 02, 2016 by Saumya Agrawal - Siemens EDA

The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
Nine Effective Features of NVMe® Questa Verification IP to Help You Verify PCIe® Based SSD Storage

Article - Mar 02, 2016 by Saurabh Sharma - Siemens EDA

This article provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to conventional technologies, and point out key areas to focus on during its verification. In particular, we will describe how NVMe Questa ® Verification IP (QVIP) effectively contributes and accelerates verification of PCIe-based SSDs that use NVMe interfaces.
MIPI C-PHY™: Man of the Hour

Article - Mar 02, 2016 by Yogesh Chaudhary - Siemens EDA

The MIPI Alliance signature dishes, C-PHY™ and D-PHY™, are becoming favorite dishes of the imaging industry. These interfaces allow system designers to easily scale up the existing MIPI Alliance Camera Serial Interface (CSI-2™) and Display Serial Interface (DSI™) ecosystems to support higher resolution image sensors and displays while keeping low power consumption at the same time. This gives them an edge to get more into the mobile systems with bigger and better pictures.
Total Recall: What to Look for in a Memory Model Library

Article - Mar 02, 2016 by Mark Peryer

Almost all electronics systems use memory components, either for storing executable software or for storing data. Accurate memory models are fundamental. Making these models available in proven, standards-based libraries is essential to functional verification of these kinds of designs.
Certus™ Silicon Debug: Don’t Prototype Without It

Article - Mar 02, 2016 by Doug Amos - Siemens EDA

Traditional FPGA debuggers might be acceptable for single FPGA designs, or where long instrumentation iterations might somehow be tolerable, but they run out of steam when faced with a full-scale, FPGA prototype of today's complex SoCs. Certus Silicon Debug is ready to take up the baton and provide prototypers with the visibility and productivity they demand.
Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows

Article - Mar 02, 2016 by Shashi Bhutada - Siemens EDA

DO-254 and other safety critical applications require meticulous initial requirements capture followed by accurate functional verification. “Elemental Analysis” in DO-254 refers to the verification completeness to ensure that all ‘elements’ of a design are actually exercised in the pre-planned testing. Code Coverage is good for checking if implementation code has been tested, but cannot guarantee functional accuracy.
Complex Signal Processing Verification under DO-254 Constraints

Article - Mar 02, 2016 by François Cerisier - AEDVICES Consulting

This article describes a combined requirement and metric driven methodology developed at a customer site for the verification of a complex signal processing SoC block under DO-254 constraints. This methodology also enables both horizontal and vertical reuse of the tests, allowing tests to run both in IP simulation and on FPGA boards at SoC level. This approach is described in a generic way and can be applied to different signal or data processing designs.
Simplifying Generation of DO-254 Compliant Verification Documents for AEH Devices

Article - Mar 02, 2016 by Hari Patel and Amarkumar Solanki - eInfochips

As per the DO-254 standard, the Airborne Electronic Hardware (AEH) needs accurate assurance of device behavior as intended within optimal operating conditions. For DAL A (Design Assurance Level A) Devices, you need to verify 100% functionality of the device and achieve 100% code coverage, including FEC.
DO-254 Compliant UVM VIP Development

Article - Mar 02, 2016 by Ates Berna - ELECTRA IC

Late 2014, we found ourselves in a Project to develop a custom interconnect UVM Compliant VIP. Not only was there a need to develop a custom UVM VIP, but there was a need to plug this to a DUT which has a PCIe and an Avalon Streaming interface on it and perform the advance verification using our custom UVM VIP.
Reusable Verification Framework

Article - Mar 02, 2016 by Gunther Clasen - Ensilica

This article demonstrates how to write interface connections only once and use them in both block- and system-level testbenches. The order is not important: System-level testbenches can be written without all the blocks of the DUT completed, DUT and UVM blocks can easily be interchanged. Taking care not to use virtual interfaces in the UVC but Bus Functional Models (BFM) in the interface instead – so called polymorphic interfaces, UVCs can be fully configurable as well as reusable.
Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse

Paper - Mar 01, 2016 by Bob Oden

With larger and more complex designs the gap between design and verification has grown larger. Because of this the reuse of the testbench both in new projects and within the same project has become very desirable. One of the "promises" of UVM is achieving such reuse. However, in reality, UVM reuse has been limited. A UVM reuse methodology will be presented that provides reuse of components from one testbench to another and within the same testbench from block to chip level.
Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse

Resource (Paper (.PDF)) - Mar 01, 2016 by Bob Oden

This paper identifies the issues that affect UVM reuse and strategies for achieving reuse.
Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse

Resource (Poster Paper) - Mar 01, 2016 by Bob Oden

This paper describes reuse techniques used in the UVM Framework. UVMF includes python-based generators for creating interface, environment and bench level code. Code generated is ready for simulation and emulation.
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis

Paper - Feb 28, 2016 by Avidan Efody

This paper deals with transient fault analysis towards ISO 26262 certification. First we suggest a way to estimate ISO 26262 required metrics with a user specified level of accuracy using statistical sampling of transient faults. We then propose a technique that reuses existing regression results in order to minimize the resources required to analyze faults in both combinatorial and sequential elements.
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis

Resource (Paper (.PDF)) - Feb 28, 2016 by Avidan Efody

Abstract-Shrinking nodes and reduced supply voltages make transient faults due to electromagnetic interferences a growing concern for mission critical ASICs and FPGAs. To address this risk, the ISO 26262 safety automotive standard requires that the impacts of transient faults on safety goals are rigorously analyzed[1]. Such analysis is far from trivial, first and foremost due to the practically infinite number of fault and state combinations that could happen in a component’s life cycle.
The Downside of Advanced Verification

Session - Feb 22, 2016 by Neil Johnson

After more than a decade, it’s become obvious the advanced verification techniques we rely on, like constrained random verification, have fallen short of their potential.
Introduction to SVUnit

Session - Feb 22, 2016 by Neil Johnson

A history of SVUnit and how it helps to directly address the poor code quality and code debug (redo) currently plaguing semiconductor teams.
Your First Unit Test!

Session - Feb 22, 2016 by Neil Johnson

See how easy it is to get started with SVUnit. Generate a unit test template, write unit tests and run them all in less than 20 minutes!
Unit Testing UVM Components

Session - Feb 22, 2016 by Neil Johnson

The ability to test UVM components is a key feature of SVUnit. We’ll generate a UVM specific unit test template, add some TLM connectivity and write a unit test to verify a simple UVM model.
An Introduction to Unit Testing with SVUnit

Track - Feb 22, 2016 by Neil Johnson

SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is the only SystemVerilog test framework suited for both design and verification engineers.
SVUnit Case Studies & Summary

Session - Feb 22, 2016 by Neil Johnson

SVUnit is being used by design and verification engineers to improve bug rates and write high quality code. We’ll look at case studies that support the use of SVUnit and summarize the case for unit testing.
Verification with Multi-core Parallel Simulations: Have You Found Your Sweet Spot Yet?

Resource (Poster Paper) - Feb 21, 2016 by Rohit Jain

This poster paper illustrates design types and applications that are suitable and not suitable for multi-core simulations.
Verification with Multi-core Parallel Simulations: Have You Found Your Sweet Spot Yet?

Resource (Paper (.PDF)) - Feb 21, 2016 by Rohit Jain

This paper is aimed at verification engineers looking to improve the productivity of their verification flow and to understand where multi-core simulations can provide maximum benefit. Successful multi-core parallel simulations depend on a variety of related design factors, which can be difficult to understand and sort out. With suitable design applications, it is possible to significantly save verification cycles.