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RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success
Article - Jun 28, 2017 by Joe Hupcey
Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. In this article we review the root cause of these challenges and introduce an automated approach to overcome these difficulties.
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Formal Verification: Not Just for Control Paths
Article - Jun 28, 2017 by Rusty Stuber - Siemens EDA
Formal property verification is sometimes considered a niche methodology ideal for control path applications. However, with a solid methodology base and upfront planning, the benefits of formal property verification, such as full path confidence and requirements based property definition, can also be leveraged for protocol driven datapaths.
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Migrating to UVM 1800.2
Chapter - Jun 24, 2017 by Verification Methodology Team
The UVM became the IEEE Standard for Universal Verification Methodology Language Reference Manual - 1800.2 in 2017
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UVM Debug
Track - Jun 14, 2017 by Tom Kiley
Design complexity continues to increase, which is contributing to new challenges in verification and debug. New solutions and methodologies (such as UVM) have emerged to address growing design complexity. Yet, even with the productivity gains that can be achieved with the adoption of UVM, newer debugging challenges specifically related to UVM need to be addressed. In this track, we examine common UVM debug issues and provide a systematic set of recommendations to effectively address them.
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UVM Debug Editor Insight
Resource (Slides (.PDF)) - Jun 14, 2017 by Harry Foster
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UVM Debug Editor Insight
Session - Jun 14, 2017 by Harry Foster
This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create the UVM debug track.
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UVM Connectivity Debug
Session - Jun 14, 2017 by Tom Kiley
In this session, we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer, viewing the values of an interface in the source and wave windows, and how to find an interface instance that is associated with a virtual interface.
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UVM Connectivity Debug
Resource (Slides (.PDF)) - Jun 14, 2017 by Tom Kiley
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UVM Phase Debug
Session - Jun 14, 2017 by Tom Kiley
In this session, we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.
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UVM Phase Debug
Resource (Slides (.PDF)) - Jun 14, 2017 by Tom Kiley
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Memory Leak Debug
Resource (Slides (.PDF)) - Jun 14, 2017 by Tom Kiley
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Memory Leak Debug
Session - Jun 14, 2017 by Tom Kiley
In this session, we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.
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UVM Configuration Database Debug
Resource (Slides (.PDF)) - Jun 14, 2017 by Tom Kiley
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UVM Configuration Database Debug
Session - Jun 14, 2017 by Tom Kiley
In this session, we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.
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Enterprise Ethernet PHY Verification
Seminar - Jun 13, 2017 by Akshay Sarup
In this session, you will learn about the wide breadth of Ethernet speeds and standards specification supported by Questa Verification IP. You will also learn about the various use models and features available in Questa VIP for verifying an Enterprise Ethernet PHY supporting the latest greatest Ethernet speeds.
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Need for Speed - PCIe® GEN4 Verification
Seminar - Jun 13, 2017 by Akshay Sarup
In this session, you will be introduced to PCI Express and the latest specification updates in PCI Express Base Specification Revision 4.0.
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Creating a Thorough Verification Environment in Less Than Two Days
Seminar - Jun 13, 2017 by Jason Polychronopoulos
In this session you will learn how to become more productive by utilizing testbench automation, testbench generation, the UVM Framework and the VIP Configurator.
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Trends and Requirements in High Speed Interface Verification
Seminar - Jun 13, 2017 by Niraj Mathur
In this session, you will learn about trends and requirements in high speed interface (HSI) verification.
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MIPI® CSI-2 TX Verification
Seminar - Jun 13, 2017 by Ivan Ristic
This session focuses on the technical details on how the verification of MIPI® CSI-2 Transmitter IP was executed using Questa Verification IPs (CSI-2 and AHB).
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Leveraging the latest DDR & Flash Memory Models
Seminar - Jun 13, 2017 by Jason Polychronopoulos
In this session, you will learn how to leverage the latest DDR and flash memory models.
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USB 3.1 Verification Challenges
Seminar - Jun 13, 2017 by Dinesh Tyagi
In this session, you will learn how to improve USB 3.1 IP quality with functional verification using SystemVerilog.
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Conquering the New IP Economy
Seminar - Jun 13, 2017 by Harry Foster
In this session, Harry Foster will present current industry trends and in both design and verification, and then introduce emerging solutions required to close the verification productivity gap.
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Breaking the Speed Limits on SoC Verification with Questa
Webinar - May 17, 2017 by Gordon Allan
In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Paper - Mar 20, 2017 by Progyna Khondkar
Since UPF was first announced in 2007 by Accellera, many of the early features- like explicit supply port, supply net and the power state table (PST)- governed UPF based low power design verification methodologies mainly from post synthesis levels and onward. However, the recent update of IEEE 1801 3 specifies intrinsic flexibility to associate a power domain with a supply set and implicate infinite ordered list of power states, augmented with incrementally refinable arguments for the objects.
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Resource (Paper (.PDF)) - Mar 20, 2017 by Progyna Khondkar
The recent edition of IEEE 1801 specifies the power state table (PST) construct should be phased out as legacy, and instead be replaced by the new semantics of the 'add_power_state' UPF command. This paper starts with investigating the limitations of legacy PST in a complex SoC design verification environment, and how to reap the benefits of the incrementally refinable power state features through the fundamental constructs of 'add_power_state'.