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Questa One (43)
VHDL (43)
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PSS (37)
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IEEE 1801 (35)
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Power Domain (33)
WRG (33)
Scoreboard (32)
ASIC (31)
DO-254 (31)
Modeling (31)
PCIe (31)
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TLM (31)
Metastability (30)
Register Model (30)
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Accellera (29)
CDC Methodology (29)
Properties (29)
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Classes (28)
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Lint (28)
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UVM Debug (28)
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Waveform (28)
Block Level (27)
Coverage Analysis (27)
Introduction to UVM (27)
Requirements Traceability (27)
Synchronization (27)
Verilog (27)
Abstraction (26)
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Property Checks (26)
U2U (26)
Archive (25)
Covergroup (25)
System Level (25)
Asynchronous Clock (24)
Cookbook (24)
DFT (24)
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Debug Methodology (24)
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Driver (24)
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Interactive Mode (24)
Netlist (24)
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Testplan (24)
UVM Basics (24)
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Chiplets (23)
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Config_db (23)
Design Complexity (23)
Design for Test (23)
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PCI Express (23)
VRM (23)
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Collaborative Analysis (22)
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DFT Verification (22)
Memory (22)
Non-Trivial Bug Escapes (22)
Proofs (22)
Signal (22)
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Constrained Random Stimulus (21)
Packages (21)
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Acceleration (20)
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C (20)
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Data Types (20)
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Functional Verification Study (20)
Hardware Fault (20)
Livesim (20)
Python (20)
Strategy (20)
X-Tracing (20)
Agentic AI (19)
Configuration Database (19)
Coverage Points (19)
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Power States (19)
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Verification Practice (19)
Verification Run Manager (19)
Virtual Interface (19)
API (18)
Advanced Debug Techniques (18)
Code Generator (18)
Controllers (18)
Gate-Level (18)
Polymorphism (18)
Sequence Item (18)
Sequencer (18)
State Space (18)
Testbench Automation (18)
Verification Effectiveness (18)
CDC Analysis (17)
Data Management (17)
Electronic Systems (17)
IC Reliability (17)
Object-Oriented Programming in SystemVerilog (17)
Reporting (17)
Sequence Driver (17)
U2U Europe (17)
UCIe (17)
Virtual Sequences (17)
BFMs (16)
Expressions (16)
Fault Simulation (16)
HLS (16)
Intelligent Automation (16)
Productivity Gap (16)
Reset-Domain Checking (16)
SLEC (16)
Sub-system (16)
Universal Chiplet Interconnect Express (16)
Class Objects (15)
Continuous Integration System (15)
Convergence (15)
Data Models (15)
Inconclusives (15)
Power Intent (15)
QVIP Configurator (15)
Stimulus Generation (15)
Validation (15)
Variable (15)
Verification Architecture (15)
X-Propagation (15)
osmosis Europe 2025 (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Coverage Models (14)
Customization (14)
Declaration (14)
FPGA Prototyping (14)
Failure Analysis (14)
Fault Grading (14)
Glitches (14)
Interconnect (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
Multi-Die (14)
NVMe (14)
Register Layer Adapter (14)
Traceability (14)
UVMC Kit (14)
Verification IQ (14)
AXI (13)
Checkers (13)
Connections (13)
Data Mining (13)
Formal Application (13)
Functional Correctness (13)
Gate-Level Simulation (13)
Hardware Acceleration (13)
Iterations (13)
Operators (13)
Python for Verification Series (13)
RDC Analysis (13)
VIQ (13)
3DIC (12)
ASIL (12)
Adoption Trends (12)
Agent (12)
Breakpoint (12)
Co-Simulation (12)
DVCon Japan (12)
Environment Pattern (12)
Hierarchical Components (12)
Implementation Model (12)
Interrupts (12)
Parameterized Classes (12)
Predictive Analysis (12)
Randomization (12)
September 2021 - Volume 17 Issue 2 (12)
Tool Assessment (12)
Unit Testing (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Configuration Object (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DPI-C (11)
Formal Verification Apps (11)
Generation (11)
High Speed (11)
Interview (11)
Isolation (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
PYUVM (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Scalable Verification (11)
Test Environment (11)
Timing (11)
Verification Process Overview (11)
AMBA (10)
Agentic Workflow (10)
Backdoor Accesses (10)
Bug Detection (10)
Class Handles (10)
Class Reference (10)
Command API (10)
Corner-case Bugs (10)
Deadlock (10)
FPU (10)
Fault Analysis (10)
HPC (10)
High-Level Synthesis (10)
Inheritance (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Metrics-Driven (10)
Model Checking (10)
Parallel Simulation (10)
Proof Coverage (10)
Property Debug (10)
RDC Methodology (10)
Reset Architecture (10)
Root of Trust (10)
Runtime (10)
SVA (10)
Safety Metrics (10)
UCDB (10)
Unified Power Format (10)
Verification Component (10)
osmosis 2025 (10)
1800.2 (9)
AI Algorithms (9)
ATPG (9)
Bitstream (9)
CDC Path (9)
CDC Protocol (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
Data Types and Procedural Statements (9)
Digital Twin (9)
Encapsulation (9)
Ethernet (9)
Formal Assertion-Based Verification (9)
Hardware Security (9)
Hierarchical Sequences (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
LLMs (9)
Learning Paths (9)
Metastable (9)
Multi-Core Architectures (9)
PSL (9)
Parameter (9)
Power Analysis (9)
Power Logic (9)
Power Optimization (9)
RDC Violations (9)
Reconvergence (9)
Reference Model (9)
Retention (9)
SPI (9)
Schematic (9)
Secure Data Path (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Specification (9)
Static Checks (9)
Structural Analysis (9)
Sub-system Level (9)
System Scaling (9)
Testbench Architecture (9)
Testing Strategies (9)
Time-to-Market (9)
Training (9)
UALink (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Waivers (9)
Whats New in Functional Verification (9)
X-Checking (9)
X-Corruption (9)
Algorithms (8)
B/C/R Script (8)
Cache Coherency (8)
Clock Gating (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
Floating-Point Units (8)
HDL Domain (8)
HTML Docs (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Mixed-Signal Design (8)
OSCI (8)
OVM2UVM (8)
Occurrence Property Pattern (8)
Overrides (8)
Phasing (8)
Pipelined (8)
Postsim (8)
Procedural Statements (8)
RTL Sign-Off (8)
Release (8)
Report (8)
Reset Tree (8)
Safety (8)
Schematic Debug (8)
Simulation Coverage (8)
State Machine (8)
State Transitions (8)
Static & Formal Adoption (8)
Supply Set (8)
TLM FIFOS (8)
Technology Scaling (8)
Test Verification (8)
UCIe 2.0 (8)
UVM Verification (8)
Verification Complete (8)
Voltage Domain Crossing (8)
XML (8)
osmosis 2023 A&D (8)
ADAS (7)
AI Model (7)
Bind (7)
Bounded Proof (7)
Clocking Verification Challenges (7)
Computational Storage (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
Coverage Measurement (7)
Data Transfer (7)
Design Assurance (7)
Design Constraints (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
Fork-Join (7)
Guidelines (7)
IP Integration (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
Layering (7)
MBIST (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Modules (7)
Monitor (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Objections (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Post-silicon Debug (7)
Power Estimation (7)
Predictors (7)
Property Analysis (7)
Prototyping (7)
Re-spins (7)
Safety Verification (7)
Sequential Analysis (7)
Siemens EDA (7)
Supply Network (7)
Test Generation (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
Transaction Recording (7)
VA Live 2023 - Huntsville (7)
Windows (7)
AEH (6)
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Agentic AI Framework (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Bugged Out Podcast (6)
Bus Protocol (6)
Callbacks (6)
Class Types (6)
Coverage Holes (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
DDR (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Mitigation (6)
Design Patterns (6)
Design Scaling (6)
Development Environment (6)
Digital Design (6)
Distributed Resource Management (6)
Electronic Hardware (6)
Fabric (6)
Flip-Flop (6)
Front and Back Door (6)
HDL (6)
HDM (6)
Hardware Designs (6)
Hierarchical Flow (6)
Implicit/Explicit (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
PCIe Gen 7 (6)
Power Efficiency (6)
Pre-Silicon (6)
Random Faults (6)
Respins (6)
Semiconductor (6)
Slave (6)
Static Analyses (6)
Stimulus Free Verification (6)
Tessent Test Solutions (6)
Transaction-Level (6)
UCIe 3.0 (6)
UVM Forum (6)
UVVM (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
VA Live 2025 - Huntsville (6)
VHDL Testbench (6)
Verbosity (6)
Verification Cycles (6)
Verification Models (6)
Visualization (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
Adaptive (5)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bins (5)
Bus Functional Models (5)
C++ (5)
CHERI (5)
Checkpoint (5)
Class Library (5)
Clock Propagation (5)
Co-Verification (5)
Concurrent Processes (5)
Constraint Solver (5)
Context-Aware Debug (5)
Control Logic (5)
Converters (5)
DAC 2024 (5)
DSP (5)
Data Encryption (5)
Debug Challenges (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Cycle (5)
Domain Specific Architectures (5)
Driver Tracing (5)
Dual Domains (5)
Error (5)
Exhaustive (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Formal Methods (5)
Formal Testbench (5)
HBM4 (5)
Hardware Verification (5)
Hardware-Assisted Verification (5)
Hierarchical Data Model (5)
High-Speed (5)
IDE (5)
IP Blocks (5)
In-Circuit Emulation (5)
Instance (5)
JEDEC (5)
Low Latency (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
MCPs (5)
March 2018 - Volume 14 Issue 1 (5)
Memory Usage (5)
NVM Express (5)
Namespaces (5)
Non-Pipelined (5)
Phases (5)
Precedence (5)
Processor Core Verification (5)
Quirky (5)
Repository (5)
SFV (5)
SSD (5)
SVUnit (5)
Sequence Library (5)
Simulink (5)
Spice (5)
Split Transactor (5)
State-Based Model (5)
Static RDC (5)
Stimulus Pattern (5)
Test Class (5)
Test Coverage (5)
Threads (5)
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Unified Coverage Database (5)
VA Live 2019 - Westford (5)
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Verbose (5)
Verification Case Document (5)
Verification Success (5)
Virtual Methods (5)
Wishbone (5)
5G (4)
BISR (4)
Bandwidth (4)
Batch and Debug (4)
Bi-Directional (4)
Bit Width (4)
Black Boxing (4)
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CXL (4)
Classifications (4)
Compute Subsystems (4)
Coverage Achievement (4)
DVFS (4)
Data Link (4)
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Deprecated (4)
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Design Hierarchy (4)
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Determinism (4)
DisplayPort (4)
Dynamic Power (4)
ECO (4)
ED-80 (4)
Enumeration (4)
Fault Coverage (4)
Fault Detection (4)
Fault List (4)
Formal Closure (4)
HBM (4)
HDMI (4)
IC Design (4)
ICE Mode (4)
IEEE (4)
Implementation Driven Formal (4)
Implementation Pattern (4)
In-Circuit Simulation (4)
In-System Test (4)
Initial States (4)
LFM (4)
Large Language Models (4)
Mathworks (4)
Metastability Injection (4)
Mitigation Architecture (4)
Non-Reset (4)
November 2018 - Volume 14 Issue 3 (4)
Objectives (4)
PCIe Gen 6 (4)
Partitioning (4)
Phase Objections (4)
Plusargs (4)
Power Constraints (4)
Protocol Checkers (4)
QEMU (4)
QoR (4)
Questa Design Solutions (4)
RTL Verification (4)
Race Conditions (4)
Register-Level Scoreboards (4)
Reset Handling (4)
Reset Signal (4)
Risk Mitigation (4)
Root Cause (4)
SVTB (4)
Security Vulnerabilities (4)
Specification Pattern (4)
Structural Checks (4)
Subscriber (4)
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Syntax (4)
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Test Plan (4)
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Time Cone (4)
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UART (4)
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UPF 4.0 (4)
USB (4)
Unreachability (4)
Use Models (4)
Utilization (4)
VA Live 2023 - Austin (4)
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VPM (4)
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Verification Blueprint (4)
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X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
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Airborne Electronic Hardware (3)
Analysis Components (3)
Analysis Port (3)
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Certification (3)
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Clock Definitions (3)
Clocking (3)
Code Quality (3)
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Cryptography (3)
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Delay Loops (3)
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ESL (3)
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FWHW (3)
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GPU (3)
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JUnit (3)
July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
LRM (3)
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NRRs (3)
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Observer (3)
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PHY (3)
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Register Assistant (3)
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Routines (3)
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Static Lists (3)
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Stream (3)
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TBX (3)
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Transfer Protocols (3)
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Type Casting (3)
UEFI (3)
UVM 1.1d (3)
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UVM Rapid Adoption (3)
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VHDL-2019 (3)
VIP - 3.1 (3)
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2D/3D (2)
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CDC Working Group (2)
CHI (2)
CSI (2)
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D-PHY (2)
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DVCON 2021 (2)
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