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Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers

Resource (Paper (.PDF)) - Dec 19, 2016 by Saurabh Sharma

NVMe is an optimized, high-performance scalable host controller interface designed to address the needs of Enterprise and Client systems that utilize PCI Express-based solid-state storage. Designed to move beyond the dark ages of hard disk drive technology, NVMe is built from the ground up for non-volatile memory (NVM) technologies.
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution

Resource (Paper (.PDF)) - Dec 19, 2016 by Saumya Agrawal

The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
The Fundamental Power States for UPF Modeling and Power Aware Verification

Resource (Paper (.PDF)) - Dec 14, 2016 by Progyna Khondkar

This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways.
The Fundamental Power States for UPF Modeling and Power Aware Verification

Paper - Dec 14, 2016 by Progyna Khondkar

This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways. Eventually the power state concept realization allows probing further into the power management components for design and IP integration in different levels of designs, from RTL to PG-netlist.
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

Webinar - Dec 05, 2016 by Kurt Takara

In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

Resource (Slides (.PDF)) - Dec 05, 2016 by Kurt Takara

In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.
How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

Webinar - Dec 05, 2016 by Mark Eslinger

In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.
FPGA Prototyping: Maximize Your Enterprise Debug Productivity

Webinar - Nov 11, 2016 by Stephen Bailey

In this session, you will learn how to maximize your enterprise debug productivity.
Industry Trends in Today’s Functional Verification Landscape

Webinar - Nov 11, 2016 by Harry Foster

In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.
Enterprise Verification Debug and Analysis

Webinar - Nov 11, 2016 by Stephen Bailey

In this session, you will learn how debug and analysis fits into a platform-based verification solution.
System Level Debug & Analysis

Webinar - Nov 11, 2016 by Gordon Allan

In this session you will learn why block level methods don't work for system level verification and why design bugs commonly escape all the way to the prototyping lab and the debug technology alternatives available to address them.
Enterprise Debug for Formal

Webinar - Nov 11, 2016 by Joe Hupcey

In this session you learn more about formal-centric enterprise debug.
Enterprise Debug for Simulation

Webinar - Nov 11, 2016 by Moses Satyasekaran

In this session, you will learn more about common debug challenges and modern debug solutions.
How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology

Article - Nov 07, 2016 by Nitish Goel - Siemens EDA

Verification environments that assist with the right set of assertions and coverpoints not only increase the verification efficiency, but also aids the verification engineer to ensure that the functionality of the IP has been met according to design specifications. This article gives insight into how to capture assertions and coverpoints and how they should be written in order to achieve maximum design verification robustness.
USB Type-C Verification: Challenges & Solution

Article - Nov 07, 2016 by Suraj Parkash Gupta, Zeeshan Yousuf - Siemens EDA

The standard USB connector that we are most familiar with is USB Type-A. Even as the USB data interface moved from USB1 to USB2 and then to USB3, the connector has remained the same. It is a massive connector and plugs in only one way.
INs and OUTs of CAN Verification: A Comprehensive UVM-based Solution

Article - Nov 07, 2016 by Saumya Agrawal - Siemens EDA

Automotive vehicles are not only fast moving, but also have various systems comprising a variety of advanced technologies. Increasing complexities of these systems need much more sophisticated components and interactions. This article explains the challenges in the verification of a CAN node and how CAN Questa Verification IP combats those.
24x7 Productivity: Veloce® Enterprise Server App Does the Job

Article - Nov 07, 2016 by Vijay Chobisa

The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario, project scheduling for the emulator was done manually by allocating fixed time slots to project teams. An inherently inflexible and inefficient way to manage a valuable resource, especially for global teams.
Power Aware Libraries: Standardization and Requirements for Questa Power Aware

Article - Nov 07, 2016 by Progyna Khondkar

Multi-voltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons.
Improving Performance and Verification of a System Through an Intelligent Testbench

Article - Nov 07, 2016 by Umesh Patel, Dhaval Shah - Arastu Systems Pvt. Ltd.

The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs.
Functional Verification Study - 2016

Session - Oct 14, 2016 by Harry Foster

In this session, Harry Foster highlights the key findings from the 2016 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy

Webinar - Sep 09, 2016 by Gordon Allan

In this session we will deliver five steps your team can take to improve first pass success, and how Questa enables your advanced verification goals every step of the way.
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Paper - Aug 26, 2016 by Kurt Takara

In this paper, we begin by discussing the low power challenges for CDC design and verification including dynamic frequency and voltage scaling (DVFS). The following section describes the low power CDC verification methods and how these methods address the low power issues. Finally, we review some application examples for low power DVFS CDC verification.
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts

Resource (Paper (.PDF)) - Aug 26, 2016 by Kurt Takara

With the advances in low power design, new low power artifacts have been introduced that cannot be detected with traditional verification techniques and may cause clock domain crossing (CDC) issues in silicon. This paper explains the new low power CDC issues and the CDC and voltage domain crossing (VDC) verification techniques developed to verify low power designs.
Extending a Traditional VIP to Solve PHY Verification Challenges

Resource (Paper (.PDF)) - Aug 26, 2016 by
Beyond UVM Registers - Better, Faster, Smarter

Paper - Aug 25, 2016 by Rich Edelman

The UVM Register package has many features. These features include reading and writing register values, reading and writing register fields and register blocks. The register model keeps track of the expected value and can directly access the actual modeled register using "back-door access". Using the register model allows a testbench to be written that can check the behavior of registers and address maps.