Search Results

Filters
Reset All

Filters

Topic

Show More

Show Less

Content Type

Show More

Show Less

Audience

Resource Type

Show More

Show Less

Tags

Show More

Show Less

2073 Results

  • Jenkins Tutorial - Setup, Install, Configuration

    Questa VRM 10.5 has native support to allow use with the Questa VRM Jenkins plug-in. This plug-in will be made available on the Jenkins plug-in website once it is released but currently has to be installed from a file. This document gathers a few notes on how to install Jenkins, install the plug-in and set-up a demo design with Jenkins running VRM.

  • JUnit Plugin (required)

  • Questa VRM

    This plugin adds the ability for Jenkins to publish results from Questa Verification Run Manager (VRM).

  • Jenkins Release

    The leading open source automation server, Jenkins provides hundreds of plugins to support building, deploying and automating any project.

  • Dashboard View (optional)

  • Five Common Pitfalls To Avoid While Verifying PCIe® Based NVMe Controllers

    NVMe is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe® based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and storage subsystems have a fundamentally different way to operate with host computers, unlike any previous storage protocol.

  • Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers

    NVMe is an optimized, high-performance scalable host controller interface designed to address the needs of Enterprise and Client systems that utilize PCI Express-based solid-state storage. Designed to move beyond the dark ages of hard disk drive technology, NVMe is built from the ground up for non-volatile memory (NVM) technologies.

  • Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution

    The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.

  • The Fundamental Power States for UPF Modeling and Power Aware Verification

    This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways.

  • The Fundamental Power States for UPF Modeling and Power Aware Verification

    This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways. Eventually the power state concept realization allows probing further into the power management components for design and IP integration in different levels of designs, from RTL to PG-netlist.

  • What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

    In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

  • What Is CDC Protocol Verification, Prevent Bugs in Your Silicon

    In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.

  • How to Shorten Your Schedule with Interactive Formal Debug and Design Exploration

    In this session, you will learn how to shorten your formal debug time and how using formal to explore design functionality.

  • FPGA Prototyping: Maximize Your Enterprise Debug Productivity

    In this session, you will learn how to maximize your enterprise debug productivity.

  • Industry Trends in Today’s Functional Verification Landscape

    In this session, you will learn more about today's industry trends in the functional verification landscape including static and dynamic verification.

  • Enterprise Verification Debug and Analysis

    In this session, you will learn how debug and analysis fits into a platform-based verification solution.

  • System Level Debug & Analysis

    In this session you will learn why block level methods don't work for system level verification and why design bugs commonly escape all the way to the prototyping lab and the debug technology alternatives available to address them.

  • Enterprise Debug for Formal

    In this session you learn more about formal-centric enterprise debug.

  • Enterprise Debug for Simulation

    In this session, you will learn more about common debug challenges and modern debug solutions.

  • INs and OUTs of CAN Verification—A Comprehensive UVM-based Solution

  • USB Type-C Verification: Challenges and Solution

  • How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology

  • 24x7 Productivity: Veloce® Enterprise Server App Does the Job

    The way companies use hardware emulation has changed. Historically, emulators were used in a lab, at one location, executing one job at a time. Because of this, an emulator often sat idle. In this scenario, project scheduling for the emulator was done manually by allocating fixed time slots to project teams. An inherently inflexible and inefficient way to manage a valuable resource, especially for global teams.

  • Power Aware Libraries: Standardization and Requirements for Questa Power Aware

    Multi-voltage (MV) based power-ware (PA) design verification and implementation methodologies require special power management attributes in libraries for standard, MV and Macro cells for two distinctive reasons.

  • Improving Performance and Verification of a System Through an Intelligent Testbench

    The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs.