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MIPI® CSI-2 TX Verification

Seminar - Jun 13, 2017 by Ivan Ristic

This session focuses on the technical details on how the verification of MIPI® CSI-2 Transmitter IP was executed using Questa Verification IPs (CSI-2 and AHB).
Leveraging the latest DDR & Flash Memory Models

Seminar - Jun 13, 2017 by Jason Polychronopoulos

In this session, you will learn how to leverage the latest DDR and flash memory models.
USB 3.1 Verification Challenges

Seminar - Jun 13, 2017 by Dinesh Tyagi

In this session, you will learn how to improve USB 3.1 IP quality with functional verification using SystemVerilog.
Conquering the New IP Economy

Seminar - Jun 13, 2017 by Harry Foster

In this session, Harry Foster will present current industry trends and in both design and verification, and then introduce emerging solutions required to close the verification productivity gap.
SoC Verification with the Questa Flow

Webinar - May 17, 2017 by Gordon Allan

In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

Paper - Mar 20, 2017 by Progyna Khondkar

Since UPF was first announced in 2007 by Accellera, many of the early features- like explicit supply port, supply net and the power state table (PST)- governed UPF based low power design verification methodologies mainly from post synthesis levels and onward. However, the recent update of IEEE 1801 3 specifies intrinsic flexibility to associate a power domain with a supply set and implicate infinite ordered list of power states, augmented with incrementally refinable arguments for the objects.
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

Resource (Paper (.PDF)) - Mar 20, 2017 by Progyna Khondkar

The recent edition of IEEE 1801 specifies the power state table (PST) construct should be phased out as legacy, and instead be replaced by the new semantics of the 'add_power_state' UPF command. This paper starts with investigating the limitations of legacy PST in a complex SoC design verification environment, and how to reap the benefits of the incrementally refinable power state features through the fundamental constructs of 'add_power_state'.
Testbench Automation - Environment

Conference - Mar 17, 2017 by Bob Oden

In this session, you will learn how to use the UVM-Framework code generation to rapidly build reusable testbench infrastructure.
Testbench Automation - Introduction

Conference - Mar 17, 2017 by Bob Oden

In this session, you will learn how to create a complex testbench that can be targeted at simulation or emulation in a couple of hours.
Testbench Automation - Testbench

Conference - Mar 17, 2017 by Bob Oden

In this session, you will learn how Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus.
Testbench Automation - Interfaces

Conference - Mar 17, 2017 by Bob Oden

In this session, you will learn how to use a VIP Configurator to shorten the bring up time for industry standard protocols.
Use Formal to Check Logic Faults

Webinar - Mar 17, 2017 by Mark Eslinger

In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.
Will Safety Critical Design Practices Improve First Silicon Success?

Article - Mar 01, 2017 by Harry Foster

For this issue of Verification Horizons, I have decided to do a deeper dive into our 2016 industry study and see what other non-intuitive observations could be uncovered. Specifically, I wanted to answer the following questions: (1) Does verification maturity impact silicon success (in terms of functional quality)? (2) Does the adoption of safety critical design practices improve silicon success?
A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products

Article - Mar 01, 2017 by Jamil R. Mazzawi, Amir N. Rahat - Optima Design Automation Ltd.

In this article, we present a simple, easy step-by-step methodology to comprehend and achieve functional safety from random faults based on Questa® simulation and the fault-injection accelerator from Optima.
Automating Tests with Portable Stimulus from IP to SoC Level

Article - Mar 01, 2017 by Matthew Ballance

Portable stimulus seeks to raise the level of abstraction and enable users to automate testing of the complex scenarios that emerge in subsystem- and SoC-level verification. However, the PSS under development by the Accellera PSWG builds on the base of constraint-based, transaction-level verification, which is already well-understood and widely deployed today.
UVM Tips and Tricks

Article - Mar 01, 2017 by Sandeep Nasa, Shankar Arora - Logic Fruit Technologies Pvt. Ltd.

UVM is the most widely used Verification methodology for functional verification of digital hardware (described using Verilog, SystemVerilog or VHDL at appropriate abstraction level). It is based on OVM and is developed by Accellera. It consists of base libraries written in SystemVerilog which enables the end user to create testbench components faster using these base libraries.
Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

Article - Mar 01, 2017 by Progyna Khondkar

The Questa Power Aware (PA) dynamic simulator (PA-SIM) provides a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from target design implementation objectives.
Complementing Functional Verification Through the Use of Available Timing Information

Article - Mar 01, 2017 by Rick Eram - Excellicon

Since the advent of formal techniques, the application of formal analysis has helped designers achieve more in-depth analysis and coverage of functional verification activities in general. However what has spurred the growth and popularity of such techniques has been specific and targeted applications of formal analysis.
How Formal Reduces Fault Analysis for ISO 26262

Paper - Feb 15, 2017 by Doug Smith

In this white paper, we will discuss how to use formal verification for static and transient fault analysis to generate the ISO 26262 safety metrics. First, we will look at some of the low-hanging fruit that formal analysis provides, and then we will discuss how to tackle the much harder task of fault injection.
How Formal Reduces Fault Analysis for ISO 26262

Resource (Paper (.PDF)) - Feb 15, 2017 by Doug Smith

This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
Questa VRM and Jenkins

Track - Jan 10, 2017 by Darron May

This track will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.
Jenkins Installation and Setup

Session - Jan 10, 2017 by Darron May

In this session you will be introduced to the Jenkins continuous integration system, along with step by step installation and setup instructions.
Jenkins Project Configuration

Session - Jan 10, 2017 by Darron May

In this session we will walk through the project configuration and how to setup a job with the Questa VRM plug-in.
Jenkins VRM Integration

Demo - Jan 10, 2017 by Darron May

In this session, we will demo the Questa VRM Jenkins integration and you will see first hand how to execute tests and generate reports.
The Fundamental Power States for UPF Modeling and Power Aware Verification

Article - Jan 04, 2017 by Verification Methodology Team