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Abstract-Concrete Class Connections
Chapter - Mar 15, 2018 by VM Team
An alternative to using a virtual interface handle for DUT to UVM testbench connections is to use an abstract-concrete class pair. The abstract version of the class defines templates for all the methods that are available in the BFM. The concrete version of the class is declared in the BFM and it extends the abstract version, providing an implementation of the methods. The handle of the concrete class is assigned to the abstract handle in the agent classes via the uvm_config_db.
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Connecting the Testbench to the DUT
Chapter - Mar 15, 2018 by VM Team
The UVM testbench objects cannot make a direct connection to the DUT signals in order to drive or sample them. The connection between an agent’s driver and monitor component objects and the DUT is indirected through one or more BFM components that have static signal ports. In this section of the UVM cookbook we consider the problem of connecting the UVM testbench to the RTL DUT.
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Messaging in Sequences
Chapter - Mar 12, 2018 by Verification Methodology Team
Sequences typically use messaging, either for debug, traceability or to report on the outcome of a built-in checking mechanism.
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Messaging
Chapter - Mar 12, 2018 by Verification Methodology Team
The UVM messaging system provides an infrastructure for printing messages in a consistent format from a UVM testbench
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UVM Report Catcher
Chapter - Mar 12, 2018 by Verification Methodology Team
There are situations where you may need to change a message generated by the messaging system, and the uvm_report_catcher is built-in call-back mechanism for doing this.
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Command-Line Verbosity Control
Chapter - Mar 12, 2018 by Verification Methodology Team
There are several UVM plusargs that can be used to control messaging verbosity, actions and severity from the command line.
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Testing Message Status
Chapter - Mar 12, 2018 by Verification Methodology Team
At the end of a UVM simulation, the report server issues a messaging summary to the transcript of the simulation.
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Using Messaging
Chapter - Mar 12, 2018 by Verification Methodology Team
The recommended way to use the UVM messaging system is to use the message macros, since they automatically insert the file name and line number of the message source into the UVM message string which is useful for debugging
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Complex Address Maps
Chapter - Mar 09, 2018 by Verification Methodology Team
In SoC design, the address mapping of registers and memory is often more complex than a single map.
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Accellera UVM 1.2 Summary
Chapter - Mar 09, 2018 by Verification Methodology Team
Cookbook topics which link to this page are affected by backwards compatibility issues or migration issues, when the Accellera UVM 1.2 release is used. Check the categories below for sources of information and advice, and a summary of the changes involved in migrating from UVM 1.1x to UVM 1.2.
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Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Webinar - Mar 07, 2018 by Ellie Burns
In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
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Questa Verification IP Integration
Session - Mar 04, 2018 by Dave Aerne
In this session, you will learn how to integrate Questa Verification IP (QVIP) within your UVMF testbench.
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Questa Verification IP Integration
Resource (Slides (.PDF)) - Mar 04, 2018 by Dave Aerne
In this session, you will learn how to integrate Questa Verification IP within your UVMF testbench.
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UVMF and Emulation
Session - Mar 04, 2018 by Mike Horn
The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.
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Configuring Memory Read Completions Sent by PCIe® QVIP
Article - Mar 01, 2018 by Arushi Jain, Rajat Rastogi - Siemens EDA
In real hardware systems, the read completion sizes for upstream read requests (initiated towards the root complex) are characteristics of the processor in use and the maximum payload size (request payload size) limitations of endpoint as a receiver. Out of various aspects to be considered while creating a read completion, important aspects of data associated with it are byte enables (valid data to be read), value of the read request, and address at which the request is initiated.
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SATA Specification 3.3 Gaps Filled by SATA QVIP
Article - Mar 01, 2018 by Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA
Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.
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Power Aware Static Verification: From Power Intent to Microarchitectural Checks of Low Power Designs - Part 1
Article - Mar 01, 2018 by Progyna Khondkar
Power Aware Static Verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).
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A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
Article - Mar 01, 2018 by Dr. Mike Bartley
This article outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs. A three-level (unit, core and SoC) hierarchy is proposed for testbenches. Each level of the hierarchical testbench is configurable for both architectural and micro-architectural parameters. At the heart of the verification strategy is an ISG (Instruction Stream Generator) and a UVM testbench.
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SVA Alternative for Complex Assertions
Article - Mar 01, 2018 by Ben Cohen
This article first explains the concepts, and then by example, how a relatively simple assertion can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as vacuity or an error in the assertion, providing examples that demonstrate how some of the SVA limitations can be overcome with the use of tasks, but yet maintain the spirit ( but not vendor’s implementations ) of SVA.
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Testbench: Architecture and Operation
Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
In this session, you will learn about the architecture of a UVMF testbench and directory structure.
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Testbench: Architecture and Operation
Session - Feb 26, 2018 by Bob Oden
The UVMF testbench contains top level modules, top level sequence, top level environment, and top-level configuration. In this session, you will learn about the architecture of a UVMF testbench and directory structure.
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Environment Code Generation
Session - Feb 26, 2018 by Jonathan Craft
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment and what parts of the generated output that you'll need to modify afterwards.
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Environment Code Generation
Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment.
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Scoreboards and Predictors
Session - Feb 26, 2018 by Bob Oden
Predictors and scoreboards provide the golden modeling and data checking function within a verification environment. In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.
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Scoreboards and Predictors
Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.