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UVM Configuration Database Debug
Session - Jun 14, 2017 by Tom Kiley
In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.
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Enterprise Ethernet PHY Verification
Seminar - Jun 13, 2017 by Akshay Sarup
In this session, you will learn about the wide breadth of Ethernet speeds and standards specification supported by Questa Verification IP. You will also learn about the various use models and features available in Questa VIP for verifying an Enterprise Ethernet PHY supporting the latest greatest Ethernet speeds.
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Need for Speed - PCIe® GEN4 Verification
Seminar - Jun 13, 2017 by Akshay Sarup
In this session, you will be introduced to PCI Express and the latest specification updates in PCI Express Base Specification Revision 4.0.
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Creating a Thorough Verification Environment in Less Than Two Days
Seminar - Jun 13, 2017 by Jason Polychronopoulos
In this session you will learn how to become more productive by utilizing testbench automation, testbench generation, the UVM Framework and the VIP Configurator.
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Trends and Requirements in High Speed Interface Verification
Seminar - Jun 13, 2017 by Niraj Mathur
In this session, you will learn about trends and requirements in high speed interface (HSI) verification.
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MIPI® CSI-2 TX Verification
Seminar - Jun 13, 2017 by Ivan Ristic
This session focuses on the technical details on how the verification of MIPI® CSI-2 Transmitter IP was executed using Questa Verification IPs (CSI-2 and AHB).
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Leveraging the latest DDR & Flash Memory Models
Seminar - Jun 13, 2017 by Jason Polychronopoulos
In this session, you will learn how to leverage the latest DDR and flash memory models.
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USB 3.1 Verification Challenges
Seminar - Jun 13, 2017 by Dinesh Tyagi
In this session, you will learn how to improve USB 3.1 IP quality with functional verification using SystemVerilog.
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Conquering the New IP Economy
Seminar - Jun 13, 2017 by Harry Foster
In this session, Harry Foster will present current industry trends and in both design and verification, and then introduce emerging solutions required to close the verification productivity gap.
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SoC Verification with the Questa Flow
Webinar - May 17, 2017 by Gordon Allan
In this session, you will learn industry best practices in verification flows and how to implement the optimal flow to speed your SoC design verification cycle.
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Sometimes the Life of a College Student and a Verification Engineer Aren’t All That Different
Article - Apr 10, 2017 by Verification Horizons
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Paper - Mar 20, 2017 by Progyna Khondkar
Since UPF was first announced in 2007 by Accellera, many of the early features- like explicit supply port, supply net and the power state table (PST)- governed UPF based low power design verification methodologies mainly from post synthesis levels and onward. However, the recent update of IEEE 1801 3 specifies intrinsic flexibility to associate a power domain with a supply set and implicate infinite ordered list of power states, augmented with incrementally refinable arguments for the objects.
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Resource (Paper (.PDF)) - Mar 20, 2017 by Progyna Khondkar
The recent edition of IEEE 1801 specifies the power state table (PST) construct should be phased out as legacy, and instead be replaced by the new semantics of the 'add_power_state' UPF command. This paper starts with investigating the limitations of legacy PST in a complex SoC design verification environment, and how to reap the benefits of the incrementally refinable power state features through the fundamental constructs of 'add_power_state'.
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Testbench Automation - Environment
Conference - Mar 17, 2017 by Bob Oden
In this session, you will learn how to use the UVM-Framework code generation to rapidly build reusable testbench infrastructure.
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Testbench Automation - Introduction
Conference - Mar 17, 2017 by Bob Oden
In this session, you will learn how to create a complex testbench that can be targeted at simulation or emulation in a couple of hours.
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Testbench Automation - Testbench
Conference - Mar 17, 2017 by Bob Oden
In this session, you will learn how Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus.
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Testbench Automation - Interfaces
Conference - Mar 17, 2017 by Bob Oden
In this session, you will learn how to use a VIP Configurator to shorten the bring up time for industry standard protocols.
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Use Formal to Check Logic Faults
Webinar - Mar 17, 2017 by Mark Eslinger
In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.
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Will Safety Critical Design Practices Improve First Silicon Success?
Article - Mar 01, 2017 by Harry Foster
For this issue of Verification Horizons, I have decided to do a deeper dive into our 2016 industry study and see what other non-intuitive observations could be uncovered. Specifically, I wanted to answer the following questions: (1) Does verification maturity impact silicon success (in terms of functional quality)? (2) Does the adoption of safety critical design practices improve silicon success?
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A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
Article - Mar 01, 2017 by Jamil R. Mazzawi, Amir N. Rahat - Optima Design Automation Ltd.
In this article, we present a simple, easy step-by-step methodology to comprehend and achieve functional safety from random faults based on Questa® simulation and the fault-injection accelerator from Optima.
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Automating Tests with Portable Stimulus from IP to SoC Level
Article - Mar 01, 2017 by Matthew Ballance
Portable stimulus seeks to raise the level of abstraction and enable users to automate testing of the complex scenarios that emerge in subsystem- and SoC-level verification. However, the PSS under development by the Accellera PSWG builds on the base of constraint-based, transaction-level verification, which is already well-understood and widely deployed today.
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UVM Tips and Tricks
Article - Mar 01, 2017 by Sandeep Nasa, Shankar Arora - Logic Fruit Technologies Pvt. Ltd.
UVM is the most widely used Verification methodology for functional verification of digital hardware (described using Verilog, SystemVerilog or VHDL at appropriate abstraction level). It is based on OVM and is developed by Accellera. It consists of base libraries written in SystemVerilog which enables the end user to create testbench components faster using these base libraries.
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Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation
Article - Mar 01, 2017 by Progyna Khondkar
The Questa Power Aware (PA) dynamic simulator (PA-SIM) provides a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from target design implementation objectives.
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Complementing Functional Verification Through the Use of Available Timing Information
Article - Mar 01, 2017 by Rick Eram - Excellicon
Since the advent of formal techniques, the application of formal analysis has helped designers achieve more in-depth analysis and coverage of functional verification activities in general. However what has spurred the growth and popularity of such techniques has been specific and targeted applications of formal analysis.
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How Formal Reduces Fault Analysis for ISO 26262
Paper - Feb 15, 2017 by Doug Smith
In this white paper, we will discuss how to use formal verification for static and transient fault analysis to generate the ISO 26262 safety metrics. First, we will look at some of the low-hanging fruit that formal analysis provides, and then we will discuss how to tackle the much harder task of fault injection.