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Comprehensive CDC Verification Using Advanced Hierarchical Data Models

Paper - Feb 28, 2019 by Ping Yeung

To help understand the importance and impact of the HDM-based hierarchical CDC flow, we will begin with a review of the existing hierarchical CDC verification methodologies. Then, we will present the improvements of the HDM-based hierarchical CDC flow and highlight its capability for verifying reconvergence of CDC paths on complex SoCs.
Boosting Regression Throughput by Reusing Setup Phase Simulation

Resource (Paper (.PDF)) - Feb 28, 2019 by Rohit Jain

This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. We will also discuss what type of designs (Verilog, VHDL, SystemVerilog, UVM-based, SystemC, C/C++ models, PLI/FLI/VPI etc.) will fit in this methodology and what a designer can do to make his design fit for such methodology.
Clock-Domain Crossing Challenges in Latch Based Designs

Resource (Paper (.PDF)) - Feb 28, 2019 by Kurt Takara

This paper describes the challenges in CDC analysis for latch-based designs and a systematic approach to handle latches that are not enabled by clock signals. It also presents the results and insights of latch-based crossings for several industrial scale designs.
Clock-Domain Crossing Challenges in Latch-Based Designs

Paper - Feb 28, 2019 by Kurt Takara

Clock-domain crossing (CDC) analysis for registers and memories are well understood problems [1] and there are many software tools to analyze the CDC issues associated with them. However, presence of latches in the designs can complicate CDC analysis as some of the latches may act as pass through combinatorial paths through which the input signal can continuously affect the output of the latch.
Low Power Apps: Shaping the Future of Low Power Verification

Resource (Paper (.PDF)) - Feb 28, 2019 by
Comprehensive CDC Verification Using Advanced Hierarchical Data Models

Resource (Paper (.PDF)) - Feb 28, 2019 by Ping Yeung

In this paper, we describe the hierarchical data model (HDM), which is the backbone of the Questa CDC hierarchical verification solution. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly reused across releases and across designs wherever the IP is reused. It can also be an performance efficient alternative to the traditional flat CDC verification flow.
Formal Techniques for Optimizing ISO 26262 Fault Analysis

Resource (Paper (.PDF)) - Feb 28, 2019 by Doug Smith

The automotive safety standard, ISO 26262 [1], states that safety analyses on hardware designs should include Failure Mode and Effects Analysis (FMEA). Hardware architectural metrics are required to assess the adequacy of the safety mechanisms and their ability to prevent faults from reaching safety critical areas. A process of fault analysis that includes fault injection is crucial for measuring and verifying the assumptions of the FMEA.
Technical Paper: Are You Smarter Than Your Testbench? With a Little Work You Can Be

Resource - Feb 28, 2019 by
Using Strong Types in SystemVerilog Design and Verification Environments

Resource (Paper (.PDF)) - Feb 28, 2019 by Dave Rich
Technical Paper: UVM Sans UVM: An Approach to Automating UVM Testbench Writing

Resource - Feb 28, 2019 by
Ten Rules to Successfully Deploy Formal

Article - Feb 25, 2019 by Dr. Ashish Darbari

About four years ago I gave a couple of talks on the myths surrounding formal. Although, formal has seen more adoption since then, we have a long way to go before it is recognized as a mainstream technology used throughout design and verification. I still see some of these myths clouding the judgement of end users and their managers.
Formal Apps Take the Bias Out of Functional Verification

Article - Feb 25, 2019 by Bill Au

When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This is why verification engineers have a blind spot for their own verification platforms. This blind spot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
Simplifying Assertion Validation Using UVM Callbacks

Article - Feb 25, 2019 by Arushi Jain - Siemens EDA

An assertion is a conditional statement that indicates the incorrect behavior of a design by flagging an error and thereby catching bugs. Assertions are used for validating a hardware design at different stages of its life-cycle, such as formal verification, dynamic validation, runtime monitoring, and emulation.
Effective Elements Lists and the Transitive Nature of UPF Commands

Article - Feb 25, 2019 by Progyna Khondkar

In this article, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inherent features help to foster and establish exact relationships between UPF and DUT objects in order to develop UPF for power management and implementation as well as conduct power aware verification.
Selecting a Portable Stimulus Application Focal Point

Article - Feb 25, 2019 by Matthew Ballance

As designs, especially System on Chip designs, have become more complex, the need for generated good, automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification.
Choosing a Format for the Portable Stimulus Specification

Resource (Paper (.PDF)) - Feb 22, 2019 by Matthew Ballance

This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms.
Low Power Verification Forum

Webinar - Feb 05, 2019 by Gordon Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Industry Advancements Required to Close the Power Management Verification Gap

Webinar - Jan 28, 2019 by Sriram Hariharan

In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
Deploying A Metrics Driven Low Power Methodology for Your RTL IP

Webinar - Jan 28, 2019 by Qazi Ahmed

In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
Low Power Verification & Analysis with Emulation

Webinar - Jan 28, 2019 by Shantanu Samant

In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
Productive Low Power Debug Across All Engines and Flows

Webinar - Jan 28, 2019 by Gordon Allan

In this session, we will answer the top nine questions asked for debugging low power in your design.
Accelerating Verification through Verification IP, Configurator and UVM Framework

Resource (Slides (.PDF)) - Jan 24, 2019 by Sharath Kannareddy
Making Verification Fun Again

Resource (Slides (.PDF)) - Jan 24, 2019 by Jonathan Craft
Verification Acceleration for FPGA Designs with Matlab

Resource (Slides (.PDF)) - Jan 24, 2019 by Jerry Grula - Siemens EDA
Welcome & Overview

Resource (Slides (.PDF)) - Jan 24, 2019 by Harry Foster