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An Emulation Strategy for AI and ML Designs

Resource (Slides (.PDF)) - Jul 15, 2019 by Vijay Chobisa

The emergence of Artificial Intelligence is the “next big thing” in the overall The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges.
Tessent: DFT Enablement for AI Devices

Conference - Jul 15, 2019 by Geir Eide

Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
Tessent: DFT Enablement for AI Devices

Resource (Slides (.PDF)) - Jul 15, 2019 by Geir Eide

In this session, we'll learn about some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed
Deep Learning Accelerator Using HLS

Resource (Slides (.PDF)) - Jul 15, 2019 by
DAC 2019 Academy PDF Presentation: Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer

Resource - Jul 15, 2019 by
DAC 2019 Academy PDF Presentation: What's Missing and What Should Be Next for SystemVerilog

Resource - Jul 15, 2019 by
Streamlining Plan & Requirements Driven Verification

Resource - Jul 12, 2019 by
Improving Verification Throughput of Today’s Complex Mixed-Signal ICs

Resource (Slides (.PDF)) - Jul 12, 2019 by
Selecting the Most Productive SoC Design Verification Techniques

Resource (Slides (.PDF)) - Jul 12, 2019 by
Veloce HYCON - OS-aware IP Development Solution

Resource (Slides (.PDF)) - Jul 12, 2019 by
RISC-V Core and SoC: Compliance, Verification, Customization

Resource (Slides (.PDF)) - Jul 11, 2019 by Larry Lapides
Emulation to Prototype - What’s Eating Your Productivity?

Resource (Slides (.PDF)) - Jul 11, 2019 by
Questa Verification IP and Portable Stimulus Maximize Your UVM Productivity

Resource (Slides (.PDF)) - Jul 11, 2019 by Tom Fitzpatrick

In this session, you will learn how you to use Portable Stimulus to leverage the built-in infrastructure in QVIP and your UVM environment to realize truly coverage-driven scenario-level functional coverage to keep you ahead of the productivity curve.
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification

Webinar - Jul 10, 2019 by Kurt Takara

This session explains the importance of a complete Clock-Domain Crossing (CDC) methodology to produce error-free silicon.
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification

Resource (Slides (.PDF)) - Jul 10, 2019 by Kurt Takara

This session explains the importance of a complete CDC methodology to produce error-free silicon.
DAC 2019 Academy PDF Presentation: Debugging Your Design in a Heterogeneous Environment

Resource - Jul 10, 2019 by
Transaction Recording & Debug with Questa & Visualizer

Webinar - Jun 20, 2019 by Rich Edelman

This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.
Integrated Approach to Power Domain/Clock-Domain Crossing Checks

Webinar - Jun 20, 2019 by Ashish Amonkar

Power Aware/CDC simulations play an important role in System Resources block verification. The session discusses overcoming challenges in making the testbench work seamlessly across NON_PA and PA configurations.
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Resource (Paper (.PDF)) - Jun 11, 2019 by Kurt Takara

Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs. This methodology is a 3-step process that provides a requirements-based approach for RDC design and verification.
A Specification-Driven Methodology for the Design and Verification of RDC Logic

Paper - Jun 11, 2019 by Kurt Takara

With the increasing complexity of today's System-on-a-Chip (SoC) designs, reset architectures have also increased in complexity. Traditional reset design and verification techniques have not evolved to address this increase in complexity. In order to avoid ad-hoc reset methods, this paper presents a specification-driven methodology to enable the design and verification of reset domain crossing (RDC) paths in large SoC designs.
Reusable UPF - Transitioning from RTL to Gate Level Verification

Resource (Paper (.PDF)) - Jun 11, 2019 by
SystemC FMU for Verification of Advanced Driver Assistance Systems

Article - Jun 03, 2019 by Keroles Khalil, Magdy A. El-Moursy - Siemens EDA

An integrated framework to simulate electronic systems (including digital and analog devices) with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting of many electronic control units (ECUs), is modeled to simulate the mechatronic system functionality. The recently developed functional mock-up interface standard approach is used to create a model for a complex cyber-physical automotive system.
Fun with UVM Sequences - Coding and Debugging

Article - Jun 03, 2019 by Rich Edelman

In a SystemVerilog UVM 2 testbench, most activity is generated from writing sequences. This article will outline how to build and write basic sequences, and then extend into more advanced usage. The reader will learn about sequences that generate sequence items; sequences that cause other sequences to occur and sequences that manage sequences on other sequencers. Sequences to generate out of order transactions will be investigated. Self-checking sequences will be written.
Creating Tests the PSS Way in SystemVerilog

Article - Jun 03, 2019 by Matthew Ballance

Portable Stimulus is one of the latest hot topics in the verification space. Siemens EDA, and other vendors, have had tools in this space for some time, and Accellera just recently released the Portable Test and Stimulus Standard, a standard language that can be used to capture Portable Stimulus semantics.
Formal Bug Hunting with “River Fishing” Techniques

Article - Jun 03, 2019 by Mark Eslinger

Formal verification has been used successfully to verify today’s SoC designs. Traditional formal verification, which starts from time 0, is good for early design verification, but it is inefficient for hunting complex functional bugs. Based on our experience, complex bugs happen when there are multiple interactions of events happening under uncommon scenarios.