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Get Your Bits Together: SystemVerilog Structures and Packages

Webinar - Jul 14, 2020 by Chris Spear

In this session, you will learn best practices for structures and packages in the SystemVerilog language and how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused.
Simplifying Questa Usage and Deployment with Qrun

Webinar - Jul 09, 2020 by Tom Kiley

In this session, you will learn how to reduce the complexity of compiling, optimizing, elaborating, and simulating your design. Qrun encapsulates the details of the QuestaSim tool invocation. Users commonly write scripts or makefiles to encapsulate these steps.
Introduction to Visualizer for the VHDL Users

Webinar - Jun 30, 2020 by Rich Edelman

This session will introduce the Visualizer Debug Environment for VHDL and UVM.
Introduction to Visualizer for the Verilog Users

Webinar - Jun 16, 2020 by Rich Edelman

This session will introduce the Visualizer Debug Environment for Verilog and UVM.
ISO 26262 Functional Safety for Autonomous Vehicles

Webinar - Jun 11, 2020 by Jake Wiltgen

When verifying safety critical systems, the stakes are raised in ensuring that bugs/defects are not introduced into production with many standards striving for zero defective parts per million. The powerful combination of Siemens EDA Functional Verification and Functional Safety products together with Siemens’ Lifecycle Management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.
Confronting Inevitability: Finding Clock and Reset Issues Before They Find You

Webinar - Jun 11, 2020 by Chris Giles

In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.
Taking SystemVerilog Arrays to the Next Dimension

Webinar - Jun 05, 2020 by Chris Spear

In this session, you will learn the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory.
Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

Webinar - Jun 04, 2020 by Joe Hupcey

In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, uncovering register policy corner cases, validating low power clock gating, late ECOs or bug fixes, or fault/SEU mitigation logic and more.
Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal

Webinar - Jun 04, 2020 by Mark Eslinger

In this session, you will learn how formal analysis works, how you can create an effective "formal testbench" with very basic, easy-to-write properties, plus an introduction to popular formal verification methodologies: bug hunting, completely proving the correctness of critical DUT functions, and proving the absence of deadlock.
Deadlock Verification For Dummies - The Easy Way Using SVA and Formal

Webinar - Jun 02, 2020 by Mark Eslinger

In this session we will show how combining the above concepts using normal SVA liveness properties allows for RTL engineers to achieve the benefit of formal deadlock analysis without the iterative component or learning a non-standard assertion language. Deadlock verification for dummies!
Better UVM Debug

Resource (Tarball) - Jun 02, 2020 by
Better UVM Debug with Visualizer

Webinar - Jun 02, 2020 by Rich Edelman

In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.
Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

Webinar - May 28, 2020 by Munish Goyal

In this session, you will learn how the Questa Verification IP library gives you everything you need to verify standard protocols in your UVM environment. With the new Configurator GUI, it's now even easier to take advantage of these powerful verification components to maximize the effectiveness of your UVM verification.
Market-Driven Trends in Hardware Emulation

Webinar - May 21, 2020 by Vijay Chobisa

In this session you will learn how AI/ML, 5G, networking and ADAS designs are affecting verification and validation and how Veloce Strato & VirtuaLAB address these verification challenges.
Context-Aware Debug for Complex Heterogeneous Environments

Webinar - May 21, 2020 by Rich Edelman

In this session, you will learn how you can debug using high level abstractions like classes, transactions, assertions, coverage, biometric search, automated temporal causality trace and how you can utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).
Productivity in the Questa Simulation Flow

Webinar - May 15, 2020 by Gordon Allan

In this session, you will learn every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.
Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs

Paper - May 15, 2020 by Kurt Takara

Metastability is a serious problem in safety-critical designs, frequently causing chips to exhibit intermittent bugs that may not be caught until an in-flight failure. Traditional simulation does not accurately analyze multi-clock designs and relies on a manual, error-prone process. This paper describes the automated clock-domain crossing verification solution DO-254 projects need and tool assessment tips.
Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs

Resource (Paper (.PDF)) - May 15, 2020 by Kurt Takara

This paper describes the automated CDC verification solution DO-254 projects need and tool assessment tips.
Optimizing Time to Bug

Webinar - May 15, 2020 by Tom Fitzpatrick

In this session, we'll be highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must now be verified and managed and the safety and security of the data and systems they control.
ISO 26262 Requirements Management

Session - Apr 21, 2020 by Jake Wiltgen

In this session, you will learn the workflow of a requirement, the artifacts that must be captured to successfully pass an assessment, and the importance of automated data management.
ISO 26262 in Simple Terms

Session - Apr 21, 2020 by Jake Wiltgen

In this session, you will gain an understanding of the core mission, scope, and key concepts of ISO 26262.
ISO 26262 in Simple Terms

Resource (Slides (.PDF)) - Apr 21, 2020 by Jacob Wiltgen
ISO 26262 Requirements Management

Resource (Slides (.PDF)) - Apr 21, 2020 by Jacob Wiltgen
Introduction to ISO 26262

Track - Apr 20, 2020 by Jake Wiltgen

The purpose of this track is to provide engineers and managers with a basic understanding of the key concepts of ISO 26262. This includes information on the scope of the standard, how the standard addresses the broader automotive supply chain, and key requirements defined at each phase of the product lifecycle.
UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know

Webinar - Apr 10, 2020 by Chris Spear

In this session, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.