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UVM Basics

Track - May 28, 2021 by Tom Fitzpatrick

UVM Basics will raise a user's level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption.
Architecting a UVM Testbench

Session - May 25, 2021 by Tom Fitzpatrick

This session covers the basic architecture of a UVM testbench, including the introduction of the Agent/UVC component.
Architecting a UVM Testbench

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Understanding the Factory and Configuration

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Understanding the Factory and Configuration

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how tests can use the factory to control the type of components that get instantiated in a UVM environment.
Modeling Transactions

Session - May 25, 2021 by Tom Fitzpatrick

This session outlines the methods needed in the design of a sequence item (a.k.a. “transaction") for use in UVM.
Modeling Transactions

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
How TLM Works

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
How TLM Works

Session - May 25, 2021 by Tom Fitzpatrick

This session discusses the use of TLM interfaces in UVM to facilitate the creation of modular, hierarchical components.
The Proper Care and Feeding of Sequences

Session - May 25, 2021 by Tom Fitzpatrick

This session covers the creation and execution of sequences, including the interaction of the sequence and driver.
The Proper Care and Feeding of Sequences

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Layered Sequences

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Layered Sequences

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to create a virtual sequence, which controls the execution of other sequences and how to model layered protocols.
Setting Up the Register Layer

Session - May 25, 2021 by Tom Fitzpatrick

This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT.
Writing and Managing Tests

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to create a set of tests derived from a base test that defines the default setup of your environment, including how to invoke specific tests from the command line.
Writing and Managing Tests

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Setting Up the Register Layer

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Using the Register Layer

Session - May 25, 2021 by Tom Fitzpatrick

This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses.
Using the Register Layer

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick

Using the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.
Register-Based Testing

Session - May 25, 2021 by Tom Fitzpatrick

This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage.
Register-Based Testing

Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
Advanced UVM

Track - May 25, 2021 by Tom Fitzpatrick

Advanced UVM builds upon the concepts covered in Basic UVM to take your UVM understanding to the next level.
The Three Witches: Preventing Glitch Nightmares on CDC Paths

Paper - May 18, 2021 by Ping Yeung

As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. To identify potential glitches at the gate level, Questa Signoff CDC uses structural CDC analysis, expression analysis, and an automated formal-based glitch detection methodology to identify real glitches in a design.
The Three Witches: Preventing Glitch Nightmares on CDC Paths

Resource (Paper (.PDF)) - May 18, 2021 by Ping Yeung

In this paper, we first explain the glitch problems in various types of CDC paths. Then we summarize an automated formal-based glitch detection methodology.
Machine Learning at the Edge: Using HLS to Optimize Power and Performance

Resource (Paper (.PDF)) - May 12, 2021 by Michael Fingeroff - Siemens EDA

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet next-generation machine learning hardware demands at the edge.