Search Results
Filters
Advanced Search
2200 Results
-
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Resource (Slides (.PDF)) - Oct 16, 2025 by Bryan Olmos - Infineon
The increasing shift towards the RISC-V open-source instruction set architecture requires the development of new design techniques. In recent years, it has been demonstrated that RISC-V designs can be generated in a modular and scalable manner by utilizing metamodeling techniques.
-
Formally Verifying Security Properties of CHERI Hardware and Software
Resource (Recording) - Oct 16, 2025 by Thomas Bauereiss - University of Cambridge
-
Formally Verifying Security Properties of CHERI Hardware and Software
Resource (Slides (.PDF)) - Oct 16, 2025 by Thomas Bauereiss - University of Cambridge
-
Harnessing AI for Real-world Hardware Verification
Resource (Slides (.PDF)) - Oct 16, 2025 by Matthew Taylor - Doulos
-
Harnessing AI for Real-world Hardware Verification
Resource (Recording) - Oct 16, 2025 by Matthew Taylor - Doulos
-
Stimulus Free Verification of a Clock Bridge Using Static and Formal
Resource (Recording) - Oct 16, 2025 by Kanthi Palaniappan - Nokia
-
Stimulus Free Verification of a Clock Bridge Using Static and Formal
Resource (Slides (.PDF)) - Oct 16, 2025 by Kanthi Palaniappan - Nokia
-
osmosis Europe 2025
Conference - Oct 16, 2025 by Nicolae Tusinschi
The osmosis Europe event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.
-
Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP
Webinar - Oct 15, 2025 by Justin Bunnell
In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges. We will then explore the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.
-
Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP
Resource (Slides (.PDF)) - Oct 15, 2025 by Justin Bunnell
In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges.
-
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
Webinar - Oct 08, 2025 by Kirolos Magdy
In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows.
-
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification
Resource (Slides (.PDF)) - Oct 08, 2025 by Kirolos Magdy
In this webinar, you will learn strategies to eliminate workflow bottlenecks and create seamless collaboration between design and verification teams and how to architect verification environments where tools, processes, and teams work in perfect harmony.
-
Interchange Format Standard in Hierarchical CDC and RDC Analysis
Resource (Verification Horizons Blog) - Oct 06, 2025 by Farhad Ahmed
For large designs with numerous asynchronous clocks and resets, there is a growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way. This allows parallelization of sub-block and noiseless analysis and helps reduce SoC runtime and speed closure of CDC and RDC issues at the SoC level.
-
Did You Know QuestaSim Supports VHDL-2019?
Resource (Slides (.PDF)) - Oct 01, 2025 by Abdelrahman Tharwat
In this webinar, we will explore the VHDL-2019 supported features in QuestaSim.
-
Did You Know QuestaSim Supports VHDL-2019?
Webinar - Oct 01, 2025 by Abdelrahman Tharwat
In this webinar, we will explore the VHDL-2019 supported features in QuestaSim such as; enhancing your VHDL testbench, accessing the host environment, assertion reporting, view modes for design configuration optimization and more.
-
Standardization of HDMs for Hierarchical CDC and RDC Analysis
Paper - Oct 01, 2025 by Farhad Ahmed
Currently HDMs must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the source of the generated model.
-
Standardization of HDMs for Hierarchical CDC and RDC Analysis
Resource (Paper (.PDF)) - Oct 01, 2025 by Farhad Ahmed
Currently HDMs must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization.
-
From Manageability to 3.0: Unlocking the Future with UCIe Verification
Resource (Verification Horizons Blog) - Sep 26, 2025 by Ujjwal Negi
The semiconductor industry is steadily moving toward multi-die integration, where chiplets from different sources are combined within a single package (known as a system in package or SiP) to deliver higher performance, scalability, and efficiency. The Universal Chiplet Interconnect Express (UCIe) standard is the backbone of this movement, offering a high-bandwidth, low-latency interconnect that enables heterogeneous chiplets to operate as one system.
-
Pushing Boundaries: Smarter Verification for UCIe Multi-die Systems
Resource (Verification Horizons Blog) - Sep 18, 2025 by Ujjwal Negi
The semiconductor industry is at a turning point. As demand for higher performance and energy efficiency continues to grow, chipmakers are moving beyond monolithic SoCs and embracing multi-die architectures. By integrating multiple dies into a single package, designers can unlock new levels of scalability, flexibility, and cost efficiency.
-
From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025
Resource (Verification Horizons Blog) - Sep 17, 2025 by Joe Hupcey
In support of Verification Academy’s educational mission, Siemens is either directly sponsoring or contributing to the following five tutorials at the upcoming DVCon Europe 2025 on Tuesday, October 14th.
-
No Reset? No Worries! Smarter Ways to Tackle RDCs to NRRs
Resource (Verification Horizons Blog) - Sep 16, 2025 by Reetika
As system-on-chip (SoC) designs continue to evolve, they’re not just expanding in size—they’re growing in complexity. Among the many challenges this evolution brings, one of the most subtle yet critical is the handling of resets. Modern architectures often juggle multiple asynchronous reset sources along with sequential elements, such as non-resettable registers (NRRs), which operate without dedicated reset pins.
-
Class is Back in Session this October: Verification Academy’s Cutting-edge Weekly Webinar Series
Resource (Verification Horizons Blog) - Sep 16, 2025 by Joe Hupcey
Verification Academy’s fall semester starts this October with the following series of weekly deep dive webinars.
-
Functional Verification Insights: A Conversation with Abhi Kolpekwar
Resource (Verification Horizons Blog) - Sep 15, 2025 by Harry Foster
Over the years, I’ve had the privilege of sharing industry data and analysis through the Siemens EDA & Wilson Research Group Functional Verification Studies . Those findings help us understand the challenges our industry faces—rising complexity, resource pressures, and declining first-silicon success rates.
-
Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs
Paper - Sep 10, 2025 by Kurt Takara
DO-254 methodologies must ensure that a device is going to behave as specified, and that everything possible is done to catch bugs before the device will be operating in flight. DO-254 projects should use an automated solution such as Questa™ CDC designed specifically for CDC verification to bridge the knowledge gap between design and verification teams, and to ensure comprehensive prevention of this problem.
-
Automating Clock-Domain Crossing Verification for DO-254 (and Other Safety-Critical) Designs
Resource (Paper (.PDF)) - Sep 10, 2025 by Kurt Takara
Metastability is a serious problem in safety-critical designs in that it frequently causes chips to exhibit intermittent failures.