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2077 Results
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Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture
Resource (Paper (.PDF)) - May 20, 2025 by Ann Keffer
This paper demonstrates an integrated, cohesive safety workflow to address the challenges of achieving ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
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Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture
Paper - May 20, 2025 by Ann Keffer
The ISO 26262 standard underscores the importance of achieving specific random hardware failure rate targets for each automotive safety integrity level and provides a comprehensive framework for assessing, mitigating, and validating random hardware failures. This paper demonstrates an integrated, cohesive safety workflow to address ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
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Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules
Conference - May 13, 2025 by Ariel Ansbacher - Veriest
In the session, we will delve into the P2S methodology, showcase its implementation using our custom compiler, and present a detailed comparison of the P2S approach versus traditional techniques across various design blocks using Questa Formal.
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Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules
Resource (Slides (.PDF)) - May 13, 2025 by Ariel Ansbacher - Veriest
This session addresses the challenges of verifying parameterized SoCs designs using Formal Verification. Traditional methods, which involve testing each parameter configuration separately, result in increased test counts, longer runtimes, and incomplete coverage.
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Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck
Resource (Slides (.PDF)) - May 13, 2025 by Elvin Serrao - Arm
In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
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Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck
Conference - May 13, 2025 by Elvin Serrao - Arm
This session demonstrates a methodology of how Questa Unreachability (UNR) flow is integrated with Verification IQ (VIQ) tool for accelerating coverage closure. In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
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Verification of a NAND flash memory controller using UVMF and CDC
Resource (Slides (.PDF)) - May 13, 2025 by Jonas Källén - Frontgrade Gaisler
This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
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Verification of a NAND flash memory controller using UVMF and CDC
Conference - May 13, 2025 by Jonas Källén - Frontgrade Gaisler
This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
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Covering Fast to Slow Frequency Crossing Analysis using Questa CDC
Resource (Slides (.PDF)) - May 13, 2025 by Amaury Breme - NXP
In the System on Chip (SoC) digital design flow, the occurrence of fast to slow crossings is a prevalent phenomenon, characterized by a source flop being clocked at a higher frequency than the destination. Such crossings pose a significant risk of inducing tangible silicon-related challenges.
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Covering Fast to Slow Frequency Crossing Analysis using Questa CDC
Conference - May 13, 2025 by Amaury Breme - NXP
This session presents a novel approach to address this gap by introducing a robust solution for conducting thorough fast to slow crossing analysis through Clock Domain Crossing (CDC) checks. By leveraging this methodology, the study aims to enhance the Quality of Results (QoR) in digital design processes, ensuring the mitigation of risks associated with fast to slow crossings.
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Functional Verification of an L2 Cache Coherent System using Avery CHI VIP
Conference - May 13, 2025 by Gregory Faux - Kalray
In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
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Functional Verification of an L2 Cache Coherent System using Avery CHI VIP
Resource (Slides (.PDF)) - May 13, 2025 by Gregory Faux - Kalray
In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
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Better Stimulus Generation Through AI
Paper - May 13, 2025 by Tom Fitzpatrick
As semiconductor designs grow increasingly complex, verification teams face mounting pressure to ensure design correctness while meeting aggressive time-to-market demands. While PSS offers powerful capabilities for creating reusable verification assets, there are perceived adoption limitations. This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Better Stimulus Generation Through AI
Resource (Paper (.PDF)) - May 13, 2025 by Tom Fitzpatrick
This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
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Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time
Resource (Paper (.PDF)) - May 13, 2025 by Sunil Sahoo
Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation.
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Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time
Paper - May 13, 2025 by Sunil Sahoo
Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation. By integrating advanced capabilities with optimized coding style improvements, SmartCompile delivers a more efficient design flow that directly addresses the challenges of modern digital design development.
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Raising the Bar in Mission-Critical Verification: Aerospace and Defense Trends Analysis of FPGA Design Practices
Resource (Paper (.PDF)) - May 13, 2025 by Harry Foster
The insights presented in this report serve as a valuable benchmark for A&D organizations aiming to evaluate and enhance their verification maturity, technology adoption, and engineering resource alignment in response to evolving challenges.
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Raising the Bar in Mission-Critical Verification: Aerospace and Defense Trends Analysis of FPGA Design Practices
Paper - May 13, 2025 by Harry Foster
The 2024 Siemens EDA and Wilson Research Group Functional Verification Study provides an in-depth analysis of current trends in FPGA design and verification, with a particular focus on the aerospace and defense (A&D) sector. The study highlights the increasing complexity of FPGA designs driven by factors such as embedded processors, asynchronous clock domains, and stringent security and safety-critical requirements.
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Turning Vision into Reality: How Questa One Fulfills the Promise of Smart Verification
Resource (Paper (.PDF)) - May 13, 2025 by Harry Foster
In this white paper, you will learn how Questa One delivers a next-generation solution engineered to turn verification from a bottleneck into a competitive advantage.
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Turning Vision into Reality: How Questa One Fulfills the Promise of Smart Verification
Paper - May 13, 2025 by Harry Foster
Verification is no longer just a step in the design flow—it’s rapidly becoming the biggest barrier to innovation. In response, Siemens offers a transformative shift toward verification that is connected, data-driven, and scalable. Questa One delivers a next-generation solution engineered to turn verification from a bottleneck into a competitive advantage.
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Questa One Unified Coverage Solution: Transforming Verification Through Intelligence
Paper - May 13, 2025 by Vladislav Palfy
The Questa One unified coverage solution introduces a fundamentally different approach to verification coverage, combining systematic verification planning with intelligent assistance to achieve coverage goals faster and more predictably, thus transforming how teams work, enabling them to collaborate closer and focus their expertise where it matters most.
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Questa One Unified Coverage Solution: Transforming Verification Through Intelligence
Resource (Paper (.PDF)) - May 13, 2025 by Vladislav Palfy
This white paper walks through the landscape of semiconductor verification have reached a critical tipping point. What was once manageable through brute force — adding more tests, more compute power, more engineers have become an unsustainable approach.
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Intent Meets Implementation: Verifying Complex Power Strategies with UPF 4.0
Paper - May 13, 2025 by Chandu Challapalli
Questa One Sim PowerAware supports several of the most commonly used features available in UPF 4.0. This white paper takes a deep dive into UPF 4.0. What’s new, why it matters and how it fits into the evolving landscape of SoC design. We’ll start with a look at how UPF has grown over the years and why version 4.0 is a significant step forward for teams building large, power-aware systems. We'll also walk through practical tips and real-world challenges that teams face when rolling out UPF 4.0.
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Intent Meets Implementation: Verifying Complex Power Strategies with UPF 4.0
Resource (Paper (.PDF)) - May 13, 2025 by Chandu Challapalli
This white paper walks through practical tips and real-world challenges that teams face when rolling out UPF 4.0.
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Accelerated Assurance with Questa One Functional Safety
Paper - May 13, 2025 by Jake Wiltgen
Engineering teams face many challenges in achieving compliance with the ISO 26262 safety standard. To meet these and remain competitive, project teams must innovate and deploy best-in-class tools and workflows. The Questa™ One functional safety solution delivers on this mission through an integrated platform, along with safety-aware AI-powered verification engines, to enable a more streamlined and efficient approach to ISO 26262 compliance.