Search Results

Advanced Search

2097 Results

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Resource (Slides (.PDF)) - May 21, 2025 by Harry Foster

In this webinar, you will discover how a connected, data-driven, and AI-enhanced approach transforms verification into a proactive, scalable system built for 3D ICs, chiplets, and software-defined architectures—delivering higher quality, faster results, and greater productivity across your engineering team.
Solving the Semiconductor Verification Crisis: From Problem to Productivity

Webinar - May 21, 2025 by Harry Foster

The semiconductor industry is facing Verification Productivity Gap 2.0 —a crisis driven by mounting design complexity, growing security demands, and workforce shortages. Traditional verification methods alone can’t keep up. This webinar explores the latest industry trends and challenges shaping functional verification, then introduces Questa One —Siemens’ smart verification platform engineered to meet these demands head-on.
Enhanced Simulation Debugging through Advanced Capabilities of Visualizer

Conference - May 20, 2025 by Satish Banukumar

In this session, you will learn what was holding our Questa Classic users back from adopting Visualizer as their debugger, even though we are sold on the advanced capabilities and performance gains, our strategy to overcome this, and then close out the talk with Visualizer features that have worked well and improvements we hope to see.
Enhanced Simulation Debugging through Advanced Capabilities of Visualizer

Resource (Slides (.PDF)) - May 20, 2025 by Satish Banukumar

This session will start with the introduction of our DUT – the advanced robotic system -- and the corresponding design and verification challenges of constantly reuse code resulting from rapid growth in the last decade.
Functional Verification Using Siemens Questa Simulation Technologies

Resource (Slides (.PDF)) - May 20, 2025 by Nirmala Balakrishnan

In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.
Functional Verification Using Siemens Questa Simulation Technologies

Conference - May 20, 2025 by Nirmala Balakrishnan

Working at the leading edge of AI Computing, with Chiplet architectures, advanced protocol and memory interfaces, it is essential that our IPs, DUTs, and functional Design Verification teams continue to scale up along with our product line and company. In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.
Shift Left using AutoCheck Formal Verification

Conference - May 20, 2025 by Mitchell Poplingher

Automated applications with formal verification under-the-hood can truly enable a “shift left”, which will be shown in this presentation on Siemens' Questa AutoCheck. In this case study, we share how this complements our simulation-based RTL verification, as it offers distinct advantages in accelerating bug detection during early RTL development stages.
Shift Left using AutoCheck Formal Verification

Resource (Slides (.PDF)) - May 20, 2025 by Mitchell Poplingher

In this session we will demonstrate automated applications with formal verification under-the-hood can truly enable a “shift left”.
Addressing the Emerging Challenges in DFT Verification with QDX

Conference - May 20, 2025 by Jake Wiltgen

The rise of AI accelerators, coupled with multi-die integration and heterogeneous architectures, has driven unprecedented complexity in semiconductor design, making advanced DFT implementations essential to meeting increasingly rigorous quality requirements. In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.
Addressing the Emerging Challenges in DFT Verification with QDX

Resource (Slides (.PDF)) - May 20, 2025 by Jake Wiltgen

In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.
Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture

Resource (Paper (.PDF)) - May 20, 2025 by Ann Keffer

This paper demonstrates an integrated, cohesive safety workflow to address the challenges of achieving ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture

Paper - May 20, 2025 by Ann Keffer

The ISO 26262 standard underscores the importance of achieving specific random hardware failure rate targets for each automotive safety integrity level and provides a comprehensive framework for assessing, mitigating, and validating random hardware failures. This paper demonstrates an integrated, cohesive safety workflow to address ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.
Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules

Conference - May 13, 2025 by Ariel Ansbacher - Veriest

In the session, we will delve into the P2S methodology, showcase its implementation using our custom compiler, and present a detailed comparison of the P2S approach versus traditional techniques across various design blocks using Questa Formal.
Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules

Resource (Slides (.PDF)) - May 13, 2025 by Ariel Ansbacher - Veriest

This session addresses the challenges of verifying parameterized SoCs designs using Formal Verification. Traditional methods, which involve testing each parameter configuration separately, result in increased test counts, longer runtimes, and incomplete coverage.
Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck

Resource (Slides (.PDF)) - May 13, 2025 by Elvin Serrao - Arm

In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck

Conference - May 13, 2025 by Elvin Serrao - Arm

This session demonstrates a methodology of how Questa Unreachability (UNR) flow is integrated with Verification IQ (VIQ) tool for accelerating coverage closure. In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.
Verification of a NAND flash memory controller using UVMF and CDC

Resource (Slides (.PDF)) - May 13, 2025 by Jonas Källén - Frontgrade Gaisler

This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
Verification of a NAND flash memory controller using UVMF and CDC

Conference - May 13, 2025 by Jonas Källén - Frontgrade Gaisler

This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.
Covering Fast to Slow Frequency Crossing Analysis using Questa CDC

Resource (Slides (.PDF)) - May 13, 2025 by Amaury Breme - NXP

In the System on Chip (SoC) digital design flow, the occurrence of fast to slow crossings is a prevalent phenomenon, characterized by a source flop being clocked at a higher frequency than the destination. Such crossings pose a significant risk of inducing tangible silicon-related challenges.
Covering Fast to Slow Frequency Crossing Analysis using Questa CDC

Conference - May 13, 2025 by Amaury Breme - NXP

This session presents a novel approach to address this gap by introducing a robust solution for conducting thorough fast to slow crossing analysis through Clock Domain Crossing (CDC) checks. By leveraging this methodology, the study aims to enhance the Quality of Results (QoR) in digital design processes, ensuring the mitigation of risks associated with fast to slow crossings.
Functional Verification of an L2 Cache Coherent System using Avery CHI VIP

Conference - May 13, 2025 by Gregory Faux - Kalray

In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
Functional Verification of an L2 Cache Coherent System using Avery CHI VIP

Resource (Slides (.PDF)) - May 13, 2025 by Gregory Faux - Kalray

In this session, you will learn more about our cache coherency background and challenges, L2 verification strategy, environment configuration, stimuli generation, metrics collection and debug.
Better Stimulus Generation Through AI

Paper - May 13, 2025 by Tom Fitzpatrick

As semiconductor designs grow increasingly complex, verification teams face mounting pressure to ensure design correctness while meeting aggressive time-to-market demands. While PSS offers powerful capabilities for creating reusable verification assets, there are perceived adoption limitations. This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
Better Stimulus Generation Through AI

Resource (Paper (.PDF)) - May 13, 2025 by Tom Fitzpatrick

This paper introduces Portable Stimulus Assist, an artificial intelligence application within the Questa One solution that transforms how verification teams learn and apply PSS.
Reach the Finish Line Faster: How Questa One Speeds Total Simulation Turnaround Time

Resource (Paper (.PDF)) - May 13, 2025 by Sunil Sahoo

Questa™ One Sim’s SmartCompile emerges as a strategic solution for reducing the overall verification timeline, offering a comprehensive set of tools that substantially reduce the turnaround time from initial compilation to final simulation.