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Without Objection: Touring the uvm_objection Implementation - Uses and Improvements
Paper - May 13, 2024 by Rich Edelman
The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that “isn't done yet.” For example, an objection can prevent a process from finishing until some other process agrees. uvm_objections are sometimes overused and are always misunderstood. This paper will explain the implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.
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On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction
Paper - May 10, 2024 by Farhad Ahmed
Reset tree checks should be viewed thoroughly before RDC analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction.
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On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction
Resource (Paper (.PDF)) - May 10, 2024 by Farhad Ahmed
This paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.
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Developing “Safe” AI Hardware
Conference - May 07, 2024 by Shaumik Ganguly - Continental
In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.
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Coverage Closure Acceleration Using Collaborative Verification IQ Tool
Conference - May 07, 2024 by Suma Ramanand - Nokia
In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.
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Optimizing Connectivity Verification Workflow with Python and Tcl Scripting
Conference - May 07, 2024 by Ariel Ansbacher - Veriest
In this session you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.
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Extraction of VC File for Physical Macro From Top VC File
Conference - May 07, 2024 by Nirav Patel - Arm
A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.
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Improving Simulation Performance Utilizing the Visualizer Profiler
Conference - May 07, 2024 by George Lloyd - Arm
In this session you will learn how Visualizer Profiler was used to identify areas for improvement within Arm VIP components and how these issues were addressed, reducing simulation time that were achieved due to these optimizations.
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Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches
Conference - May 07, 2024 by Espen Tallaksen - EmLogic
In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).
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Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend
Conference - May 07, 2024 by Mihajlo Katona - Veriest
In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method.
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New AI Horizons in Static & Formal Verification
Resource (Recording) - Apr 24, 2024 by Dan Yu
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New AI Horizons in Static & Formal Verification
Resource (Slides (.PDF)) - Apr 24, 2024 by Dan Yu
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Optimizing FPGA Equivalence Checking for A&D Designs
Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Urish
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Driving Efficient Execution with Continuous Integration
Resource (Slides (.PDF)) - Apr 24, 2024 by Kevin Campbell
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Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance
Resource (Slides (.PDF)) - Apr 24, 2024 by Dr. Jonathan Graf
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osmosis Aerospace and Defense 2024
Conference - Apr 24, 2024 by John Hallman
osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
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Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim
Resource (Slides (.PDF)) - Apr 16, 2024 by Rich Edelman
In this webinar we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size.
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Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim
Webinar - Apr 16, 2024 by Rich Edelman
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.
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Techniques to Identify Reset Metastability Due to Soft Resets
Resource (Paper (.PDF)) - Apr 15, 2024 by Reetika
In this paper, we present a systematic methodology, as a part of static analysis, to intelligently identify critical reset domain bugs associated with soft resets. A soft reset is a mechanism that initiates a controlled reset within the system without fully powering it off.
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Techniques to Identify Reset Metastability Due to Soft Resets
Paper - Apr 15, 2024 by Reetika
Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. In this paper, we present a systematic methodology, as a part of static analysis, to intelligently identify critical reset-domain bugs associated with soft resets. A soft reset is a mechanism that initiates a controlled reset within the system without fully powering it off.
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Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench
Conference - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA
It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.
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Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench
Resource (Slides (.PDF)) - Apr 04, 2024 by Salil Pandit, Robert Rice - Siemens EDA
It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.
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Why and How We Migrated from In-house Regression Management and Coverage Flow to Verification IQ
Conference - Apr 04, 2024 by Avinash Agrawal - Siemens EDA
In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
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Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ
Resource (Slides (.PDF)) - Apr 04, 2024 by Avinash Agrawal - Siemens EDA
In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
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How and Why We Adopted Questa Core in the Development of Quantum Computers
Conference - Apr 04, 2024 by Jan Marjanovic - Atom Computing
This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.